Anton Lydike
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57f827ba6a
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updated version to 2.0.0a2
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2022-03-27 20:24:26 +02:00 |
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Anton Lydike
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b5e20ed39b
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added docstrings to Int32 and UInt32 classes
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2022-03-27 20:22:31 +02:00 |
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Anton Lydike
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4ca475da69
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improved the MMU.translate_address function
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2022-03-27 20:22:11 +02:00 |
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Anton Lydike
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cc3df91fd1
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[restructured] moved more types and exceptions to riscemu.types
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2022-03-27 19:11:10 +02:00 |
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Anton Lydike
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bc26ed3a02
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[restructured] moved all simple type definitions into riscemu.types
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2022-03-27 19:06:23 +02:00 |
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Anton Lydike
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254410e9cc
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[priv] fixed error in halt csr
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2022-03-27 18:45:59 +02:00 |
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Anton Lydike
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26d0a165f7
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[priv] added --slowdown flag to slow down emulated clock speed
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2022-03-27 18:45:28 +02:00 |
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Anton Lydike
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cadccaef00
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[priv] fixed printing for mret, sret and uret
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2022-03-27 18:44:41 +02:00 |
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Anton Lydike
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71093fe72f
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Maor round of bugfixes and incremental improvements
- fixed errors in TextIO and IOModule
- moved to Int32 and UInt32 based arithmetic
- added a lot of end-to-end and other tests
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2022-03-27 15:21:10 +02:00 |
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Anton Lydike
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cd5795bb74
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fixed priv start code, added tests
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2022-02-18 10:17:12 +01:00 |
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Anton Lydike
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4f1c73df9e
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various small bugfixes
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2022-02-13 19:44:56 +01:00 |
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Anton Lydike
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881f4004ed
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fixed removed argparse line in riscemu.__init__.py
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2022-02-13 19:43:44 +01:00 |
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Anton Lydike
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6fa3558f6c
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added interactive mode, fixed some bugs
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2022-02-13 14:55:03 +01:00 |
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Anton Lydike
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3d2619c258
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created a better output for reads/writes outside of known regions
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2022-02-11 20:29:11 +01:00 |
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Anton Lydike
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185ae8b94e
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added config and better loading code to CPU base
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2022-02-11 20:25:19 +01:00 |
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Anton Lydike
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2880a59dbb
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fixed ascii escape sequences and section address calculation
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2022-02-11 18:53:26 +01:00 |
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Anton Lydike
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7904a4dae8
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added verbosity control to user mode emulator
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2022-02-11 18:31:23 +01:00 |
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Anton Lydike
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b396e0c5eb
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user mode emulator finally working again
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2022-02-11 18:27:10 +01:00 |
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Anton Lydike
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5538034f8b
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started with base type overhaul
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2022-02-11 13:32:02 +01:00 |
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Anton Lydike
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0488a9d6bc
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finished basic RISC-V parser
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2022-01-18 21:08:07 +01:00 |
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Anton Lydike
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dc4dca6fea
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[wip] almost done with the rework of the parser and internal data structure representation of programs
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2021-12-18 00:25:39 +01:00 |
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Anton Lydike
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d5a4acef67
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tokenizer reimplemented
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2021-12-13 23:23:55 +01:00 |
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Anton Lydike
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52e189c226
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fixed missing newline at the end of the file
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2021-12-10 13:46:57 +01:00 |
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Anton Lydike
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b317974dcc
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made sure register values adhere to correct 32bit two's complement standard - fixes #4
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2021-12-10 13:25:22 +01:00 |
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Anton Lydike
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a0259707b2
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Released v1.0.0 to PyPi
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2021-12-05 21:17:05 +01:00 |
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Anton Lydike
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e65775774a
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extended userspace RV32I with li, la and mv instruction
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2021-12-05 16:45:06 +01:00 |
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Anton Lydike
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e9c11e9a41
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added correct instruction printing
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2021-11-16 08:02:27 +01:00 |
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Anton Lydike
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0b34aea520
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Merge pull request #1 from AntonLydike/kernel-mode
Adding limited privileged emulation using the `riscemu.priv` module
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2021-10-10 19:58:35 +02:00 |
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Anton Lydike
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7ab3f8361d
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code cleanup to increase visibility
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2021-09-30 22:04:49 +02:00 |
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Anton Lydike
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d09b7a5cb1
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overhaul of debugging info printing
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2021-09-30 21:54:50 +02:00 |
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Anton Lydike
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d0c5abe845
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added a whole lot of debugging info for privileged emulation
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2021-09-30 20:58:44 +02:00 |
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Anton Lydike
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3d4d36bfe4
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moved dependency on pyelftools into scoped function where it's used to reduce the number of dependencies required overall
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2021-09-03 15:01:55 +02:00 |
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Anton Lydike
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0c96a87dcb
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added RV32A extension, only missing LR.W and SC.W
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2021-09-03 14:59:34 +02:00 |
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Anton Lydike
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3033eb9985
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tranlsation from absolute addressed to symbol-relative names for debugging
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2021-08-30 20:10:22 +02:00 |
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Anton Lydike
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ca71e196c2
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added verbose flag and improved verbose output
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2021-08-30 19:40:13 +02:00 |
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Anton Lydike
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f2d07f90b5
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priv: added __main__ script to module which correctly configures the cpu depending on --kernel or --image options
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2021-08-30 15:40:13 +02:00 |
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Anton Lydike
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0651eabe18
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fixed how ecalls are represented and handled
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2021-08-30 15:09:31 +02:00 |
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Anton Lydike
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684c858300
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added support for IO modules
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2021-08-26 10:48:26 +02:00 |
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Anton Lydike
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df9e610d14
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forgot to commit image loader code
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2021-08-26 10:47:47 +02:00 |
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Anton Lydike
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1f03449694
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added memory image support to priv emulator
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2021-08-26 10:46:06 +02:00 |
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Anton Lydike
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4c352d8567
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[MMU] caching last used code section
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2021-06-08 16:34:45 +02:00 |
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Anton Lydike
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e8685af328
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[PrivMMU] cleaned up file formatting
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2021-06-08 16:34:19 +02:00 |
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Anton Lydike
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3d07c97a52
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[PrivCPU] improved step function performance by checking time every tenth cycle
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2021-06-08 16:33:48 +02:00 |
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Anton Lydike
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60a2a8d546
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[CSR] adding cache to mstatus register
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2021-06-08 16:32:39 +02:00 |
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Anton Lydike
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6b4f38d030
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[ElfLoader] added cache for already decoded instructions
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2021-06-08 15:07:51 +02:00 |
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Anton Lydike
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05c17bc029
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[PrivCPU] fixed debugger skipping over ebreak instructions
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2021-06-08 14:44:13 +02:00 |
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Anton Lydike
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baa1f24eb7
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[CpuTraps] fixed formatting for mcause registers
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2021-06-08 14:42:44 +02:00 |
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Anton Lydike
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777717ed2e
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[PrivRV32I] fixed csrrw instruction to correctly switch register contents
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2021-06-08 11:36:33 +02:00 |
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Anton Lydike
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c7b3693740
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[Regsietrs] ensuring register values are 32bit
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2021-06-08 11:36:00 +02:00 |
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Anton Lydike
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cc598c0910
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[PrivCPU] changed timer compare to lower equals to trigger exactly on time
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2021-06-08 11:35:20 +02:00 |
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Anton Lydike
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affaa60d22
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[PrivCPU] adding performance counter
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2021-06-08 11:34:28 +02:00 |
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Anton Lydike
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48ce44993b
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[CSR] Adding dump_mstatus method to csr
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2021-06-08 11:32:51 +02:00 |
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Anton Lydike
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639f91b192
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[decoder] removed sign extension for CSR type instructions
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2021-06-08 11:31:58 +02:00 |
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Anton Lydike
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c25b9f2343
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[PrivCPU] implemented CPU interrupt handling context switch
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2021-06-08 00:23:09 +02:00 |
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Anton Lydike
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4c7f3ffe67
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[PrivCPU] fixed perf-counter not comparing against shifted time
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2021-06-08 00:22:30 +02:00 |
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Anton Lydike
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c2002cd46d
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[PrivCPU] fixed naming for csr mtimecmp callback function
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2021-06-08 00:21:51 +02:00 |
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Anton Lydike
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5b2b12507d
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[PrivRV32I] added half od csrrs instruction (reading only)
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2021-06-08 00:21:05 +02:00 |
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Anton Lydike
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052ad56310
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[CSR] fixed call to enum value member
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2021-06-08 00:20:25 +02:00 |
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Anton Lydike
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d9e5d78f87
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[Registers] removed info when writing to zero register
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2021-06-08 00:19:36 +02:00 |
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Anton Lydike
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79d913baaf
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[decoder] fixed formatting in print_ins function
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2021-06-08 00:19:04 +02:00 |
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Anton Lydike
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9278235e44
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[decoder] fixed botched j immediate decoding
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2021-06-08 00:18:44 +02:00 |
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Anton Lydike
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6351f1e84d
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[PrivRV32I] fixed bug with blt backwards jumps missing by one
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2021-06-06 09:55:15 +02:00 |
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Anton Lydike
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f14bd2b983
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[PrivCPU, PrivRV32I] fixed bug where ebreaks where missed during debugging
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2021-06-05 16:19:35 +02:00 |
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Anton Lydike
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c1110b9ce3
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[ElfLoader] better formatting for jump and load/store instructions
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2021-06-05 15:29:40 +02:00 |
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Anton Lydike
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37910018b9
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[PrivRV32I] finally correct parsing of load/store instruction args
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2021-06-05 15:29:06 +02:00 |
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Anton Lydike
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e4537f86d9
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[PrivRV32I] implemented csrrwi instruction
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2021-06-05 15:28:27 +02:00 |
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Anton Lydike
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c770cc05cf
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[Priv Exceptions] added __str__ as __repr__ alias to CpuTrap to correctly format exceptions when printed
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2021-06-05 15:25:39 +02:00 |
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Anton Lydike
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3e4920f5d9
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[decoder] fixed bug when decoding add/sub instruction
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2021-06-05 15:24:40 +02:00 |
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Anton Lydike
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849d5f4fc3
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[decoder, ElfLoader] decoing an instruction now returns all args as int
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2021-06-05 15:24:16 +02:00 |
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Anton Lydike
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f9b0bac245
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[Priv Exceptions] fixed constructor typo in TimerInterrupt
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2021-06-05 09:56:05 +02:00 |
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Anton Lydike
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9424390b65
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[decoder] Added mret, sret, uret, wfi instruction decoding support
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2021-06-05 09:54:58 +02:00 |
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Anton Lydike
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198d14d5fb
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[Priv Exceptions] added __repr__ to CpuTrap class
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2021-06-05 09:29:20 +02:00 |
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Anton Lydike
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ca3b4099d4
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[Priv] moved CSR constants to a separate file
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2021-06-05 09:27:03 +02:00 |
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79369889f4
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[CSR] fixed method naming for _addr_to_name (now _name_to_addr)
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2021-06-04 20:37:08 +02:00 |
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de261c4c43
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[Priv] overhauled instruction architecture
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2021-06-04 20:36:33 +02:00 |
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c963fe3989
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[Priv] small fixes for overlooked things
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2021-05-26 18:40:42 +02:00 |
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85af9b992f
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[PrivCPU] overhaul of instruction cycle, adding more CSR interaction
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2021-05-25 23:50:38 +02:00 |
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7239212729
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[CSR] adding virtual csr registers
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2021-05-25 23:49:37 +02:00 |
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6653ef7e7c
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[CPU] set correct MISA
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2021-05-25 11:14:52 +02:00 |
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a1f29b9d97
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[CPU] cleaned up constructor
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2021-05-25 11:14:18 +02:00 |
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49b59cd46a
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[CSR] added read/write checks and unified name to addr resuloution
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2021-05-25 10:49:54 +02:00 |
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291f44a192
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[CSR] unknown csr names now fail without exception
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2021-05-25 10:24:24 +02:00 |
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c4cd83701f
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[CSR, PrivCPU] Added csr callback registration through decorator
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2021-05-24 15:51:05 +02:00 |
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504407c0d9
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[CSR] adding callbacks to each csr block
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2021-05-24 14:34:35 +02:00 |
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Anton Lydike
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db2b0b314b
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[PrivCPU, PrivRV32I] fix for relative jumps and branches
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2021-05-24 10:08:53 +02:00 |
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Anton Lydike
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6bd5cd1598
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[ElfLoader] better formatting for load and save instructions
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2021-05-24 10:08:01 +02:00 |
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Anton Lydike
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ed6912a060
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[ElfLoader] added bounds check to elf loader and casting binary data to bytearray
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2021-05-24 10:07:21 +02:00 |
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Anton Lydike
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55be71dcc3
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[CSR] added time and timeh csr codes
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2021-05-24 10:05:34 +02:00 |
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Anton Lydike
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3a79bfdada
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[ElfLoader] also loading .sdata and .sbss sections now
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2021-05-23 12:59:59 +02:00 |
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Anton Lydike
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3f11cd84ca
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[decoder] fixed error with decoding slli type instructions
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2021-05-23 12:58:47 +02:00 |
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Anton Lydike
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f3959be843
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[decoder] now returning instruction number as third return value
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2021-05-23 10:44:27 +02:00 |
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Anton Lydike
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0475d8d384
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[CPU] added instruction XLEN attribute to CPU class to support multiple instruction lengths
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2021-05-23 10:42:04 +02:00 |
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Anton Lydike
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c9a136d595
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[instructions] fixed error in auipc command
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2021-05-22 21:05:14 +02:00 |
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Anton Lydike
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ee0aac30c4
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[instructions] moved regs and mmu to properties to work with janky PrivCPU
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2021-05-22 21:04:43 +02:00 |
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Anton Lydike
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1bdf2e6efe
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[mmu] fixed typo in docstring
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2021-05-22 21:03:56 +02:00 |
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Anton Lydike
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c48a5efee3
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[cpu] fixed formatting to include cpu class extensions
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2021-05-22 21:03:37 +02:00 |
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Anton Lydike
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15da68995c
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[priv] module now able to load and execute elf binaries
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2021-05-22 21:02:36 +02:00 |
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Anton Lydike
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a4735db388
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Added a decoder module which can deocde some RV32I/M instructions
Some of them even correctly O.o
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2021-05-22 21:01:03 +02:00 |
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Anton Lydike
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483a3f2416
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Priv: [wip] implementing privileged architecture
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2021-05-19 12:14:43 +02:00 |
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Anton Lydike
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a2e206eaee
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renamed CPU.__run -> CPU._run, it's now overwriteable by subclasses
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2021-05-19 09:51:51 +02:00 |
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