[PrivRV32I] finally correct parsing of load/store instruction args

2021-06-05 15:29:06 +02:00 · 2021-06-05 15:29:06 +02:00 · 37910018b9
commit 37910018b9
parent e4537f86d9
1 changed files with 3 additions and 1 deletions
--- a/riscemu/priv/PrivRV32I.py
+++ b/riscemu/priv/PrivRV32I.py
@ -138,4 +138,6 @@ class PrivRV32I(RV32I):

    def parse_mem_ins(self, ins: 'LoadedInstruction') -> Tuple[str, int]:
        ASSERT_LEN(ins.args, 3)
-        return ins.get_reg(1), self.get_reg_content(ins, 0) + ins.get_imm(2)
+        addr = self.get_reg_content(ins, 1) + ins.get_imm(2)
+        reg = ins.get_reg(0)
+        return reg, addr