Priv: [wip] implementing privileged architecture
Anton Lydike
4 years ago
parent
a2e206eaee
commit
483a3f2416
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from typing import Dict, Union
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from collections import defaultdict
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MSTATUS_OFFSETS = {
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'uie': 0,
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'sie': 1,
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'mie': 3,
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'upie': 4,
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'spie': 5,
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'mpie': 7,
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'spp': 8,
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'mpp': 11,
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'fs': 13,
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'xs': 15,
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'mpriv': 17,
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'sum': 18,
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'mxr': 19,
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'tvm': 20,
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'tw': 21,
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'tsr': 22,
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'sd': 31
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}
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"""
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Offsets for all mstatus bits
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"""
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MSTATUS_LEN_2 = ('mpp', 'fs', 'xs')
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"""
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All mstatus parts that have length 2. All other mstatus parts have length 1
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"""
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class CSR:
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"""
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This holds all Control and Status Registers (CSR)
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"""
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regs: Dict[int, int]
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"""
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All Control and Status Registers are stored here
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"""
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name_to_addr: Dict[str, int] = {
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'mstatus': 0x300,
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'misa': 0x301,
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'mie': 0x304,
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'mtvec': 0x305,
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'mepc': 0x341,
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'mcause': 0x342,
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'mtval': 0x343,
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'mip': 0x344,
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'mvendorid': 0xF11,
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'marchid': 0xF12,
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'mimpid': 0xF13,
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'mhartid': 0xF14,
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}
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"""
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Translation for named registers
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"""
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def __init__(self):
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self.regs = defaultdict(lambda: 0)
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def set(self, addr: Union[str, int], val: int):
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if isinstance(addr, str):
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if not addr in self.name_to_addr:
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print("Unknown CSR register {}".format(addr))
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addr = self.name_to_addr[addr]
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self.regs[addr] = val
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def get(self, addr: Union[str, int]):
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if isinstance(addr, str):
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if not addr in self.name_to_addr:
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print("Unknown CSR register {}".format(addr))
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addr = self.name_to_addr[addr]
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return self.regs[addr]
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# mstatus properties
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def set_mstatus(self, name: str, val: int):
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"""
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Set mstatus bits using this helper. mstatus is a 32 bit register, holding various machine status flags
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Setting them by hand is super painful, so this helper allows you to set specific bits.
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Please make sure your supplied value has the correct width!
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:param name:
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:param val:
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:return:
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"""
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size = 2 if name in MSTATUS_LEN_2 else 1
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off = MSTATUS_OFFSETS[name]
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mask = (2**size - 1) << off
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old_val = self.get('mstatus')
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erased = old_val & (~mask)
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new_val = erased | (val << off)
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self.set('mstatus', new_val)
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def get_mstatus(self, name):
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size = 2 if name in MSTATUS_LEN_2 else 1
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off = MSTATUS_OFFSETS[name]
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mask = (2**size - 1) << off
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return (self.get('mstatus') & mask) >> off
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from ..Executable import Executable, MemorySection, MemoryFlags
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# This requires pyelftools package!
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class ElfExecutable(Executable):
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def __init__(self, name):
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from elftools.elf.elffile import ELFFile
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with open(f)
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from typing import Optional
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class CpuTrap(BaseException):
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code: int
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interrupt: int
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mtval: int
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def __init__(self, interrupt: int, code: int, mtval=0):
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assert 0 <= interrupt <= 1
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self.interrupt = interrupt
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self.code = code
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self.mtval = mtval
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@property
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def mcause(self):
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return (self.code << 31) + self.interrupt
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class IllegalInstructionTrap(CpuTrap):
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def __init__(self):
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super().__init__(0, 2, 0)
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"""
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RiscEmu (c) 2021 Anton Lydike
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SPDX-License-Identifier: MIT
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"""
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from riscemu.CPU import *
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from enum import IntEnum
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from riscemu.Executable import LoadedMemorySection
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from .Exceptions import *
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from .CSR import CSR
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from .PrivRV32I import PrivRV32I
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from ..instructions.RV32M import RV32M
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from collections import defaultdict
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from typing import Union
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if typing.TYPE_CHECKING:
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from riscemu import Executable, LoadedExecutable, LoadedInstruction
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from riscemu.instructions.InstructionSet import InstructionSet
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class PrivModes(IntEnum):
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USER = 0
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SUPER = 1
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MACHINE = 3
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class PrivCPU(CPU):
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"""
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This is a CPU that has different modes, instruction sets and registers.
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It should support M and U Mode, but no U-Mode Traps.
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This allows us to
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"""
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csr: CSR
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INS_XLEN = 1
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"""
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Size of an instruction in memory. Should be 4, but since our loading code is shit, instruction take up
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the equivalent of "1 byte" (this is actually impossible)
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"""
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def __init__(self, conf):
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super().__init__(conf, [PrivRV32I, RV32M])
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self.mode: PrivModes = PrivModes.MACHINE
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# set up CSR
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self.csr = CSR()
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# TODO: Actually populate the CSR with real data (vendorID, heartID, machine implementation etc)
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self.csr.set('mhartid', 0) # core id
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self.csr.set('mimpid', 1) # implementation id
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self.csr.set('misa', ()) # available ISA
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def _run(self, verbose=False):
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if self.pc <= 0:
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return False
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ins = None
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try:
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while not self.exit:
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try:
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self.cycle += 1
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ins = self.mmu.read_ins(self.pc)
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if verbose:
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print(FMT_CPU + " Running 0x{:08X}:{} {}".format(self.pc, FMT_NONE, ins))
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self.pc += 1
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self.run_instruction(ins)
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except CpuTrap as trap:
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mie = self.csr.get_mstatus('mie')
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if not mie:
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print("Caught trap while mie={}!".format(mie))
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# TODO: handle this a lot better
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continue
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# raise trap
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# caught a trap!
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self.csr.set('mepc', self.pc) # store MEPC
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self.csr.set_mstatus('mpp', self.mode) # save mpp
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self.csr.set_mstatus('mpie', mie) # save mie
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self.csr.set_mstatus('mie', 0) # disable further interrupts
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self.csr.set('mcause', trap.mcause) # store cause
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# set mtval csr
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self.csr.set('mtval', trap.mtval)
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# set priv mode to machine
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self.mode = PrivModes.MACHINE
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# trap vector
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mtvec = self.csr.get('mtvec')
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if mtvec & 3 == 1:
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# vectored mode!
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self.pc = (mtvec >> 2) + (self.INS_XLEN * trap.code)
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else:
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# standard mode
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self.pc = (mtvec >> 2)
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except RiscemuBaseException as ex:
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if not isinstance(ex, LaunchDebuggerException):
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print(FMT_ERROR + "[CPU] excpetion caught at 0x{:08X}: {}:".format(self.pc - 1, ins) + FMT_NONE)
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print(ex.message())
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self.pc -= 1
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if self.active_debug:
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print(FMT_CPU + "[CPU] Returning to debugger!" + FMT_NONE)
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return
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if self.conf.debug_on_exception:
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launch_debug_session(self, self.mmu, self.regs,
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"Exception encountered, launching debug:")
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if self.exit:
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print()
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print(FMT_CPU + "Program exited with code {}".format(self.exit_code) + FMT_NONE)
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sys.exit(self.exit_code)
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else:
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print()
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print(FMT_CPU + "Program stopped without exiting - perhaps you stopped the debugger?" + FMT_NONE)
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@ -0,0 +1,79 @@
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"""
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RiscEmu (c) 2021 Anton Lydike
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SPDX-License-Identifier: MIT
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"""
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from riscemu.instructions.RV32I import *
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from ..Exceptions import INS_NOT_IMPLEMENTED
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from riscemu.priv.PrivCPU import PrivModes, PrivCPU
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from .Exceptions import *
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class PrivRV32I(RV32I):
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cpu: PrivCPU
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"""
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This is an extension of RV32I, written for the PrivCPU class
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"""
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def instruction_csrrw(self, ins: 'LoadedInstruction'):
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rd, off, rs = self.parse_crs_ins(ins)
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if rd != 'zero':
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old_val = int_from_bytes(self.cpu.csr.read(off, 4))
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self.regs.set(rd, old_val)
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self.cpu.csr.write(off, 4, int_to_bytes(rs))
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def instruction_csrrs(self, ins: 'LoadedInstruction'):
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INS_NOT_IMPLEMENTED(ins)
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def instruction_csrrc(self, ins: 'LoadedInstruction'):
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INS_NOT_IMPLEMENTED(ins)
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def instruction_csrrsi(self, ins: 'LoadedInstruction'):
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INS_NOT_IMPLEMENTED(ins)
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def instruction_csrrwi(self, ins: 'LoadedInstruction'):
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INS_NOT_IMPLEMENTED(ins)
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def instruction_csrrci(self, ins: 'LoadedInstruction'):
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INS_NOT_IMPLEMENTED(ins)
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def instruction_mret(self, ins: 'LoadedInstruction'):
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if self.cpu.mode != PrivModes.MACHINE:
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print("MRET not inside machine level code!")
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raise IllegalInstructionTrap()
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# retore mie
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mpie = self.cpu.csr.get_mstatus('mpie')
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self.cpu.csr.set_mstatus('mie', mpie)
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# restore priv
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mpp = self.cpu.csr.get_mstatus('mpp')
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self.cpu.mode = PrivModes(mpp)
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# restore pc
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mepc = self.cpu.csr.get('mepc')
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self.cpu.pc = mepc
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def instruction_uret(self, ins: 'LoadedInstruction'):
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raise IllegalInstructionTrap()
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def instruction_sret(self, ins: 'LoadedInstruction'):
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raise IllegalInstructionTrap()
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def instruction_scall(self, ins: 'LoadedInstruction'):
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"""
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Overwrite the scall from userspace RV32I
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"""
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if self.cpu.mode == PrivModes.USER:
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raise CpuTrap(0, 8) # ecall from U mode
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elif self.cpu.mode == PrivModes.SUPER:
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raise CpuTrap(0, 9) # ecall from S mode - should not happen
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elif self.cpu.mode == PrivModes.MACHINE:
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raise CpuTrap(0, 11) # ecall from M mode
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def parse_crs_ins(self, ins: 'LoadedInstruction'):
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ASSERT_LEN(ins.args, 3)
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return ins.get_reg(0), ins.get_imm(1), self.get_reg_content(ins, 2)
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@ -0,0 +1,15 @@
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"""
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RiscEmu (c) 2021 Anton Lydike
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SPDX-License-Identifier: MIT
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The priv Module holds everything necessary for emulating privileged risc-v assembly
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Running priv is only preferable to the normal userspace emulator, if you actually want to emulate the whole system.
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Syscalls will have to be intercepted by your assembly code.
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The PrivCPU Implements the Risc-V M/U Model, meaning there is machine mode and user mode. No PMP or paging is available.
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"""
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@ -0,0 +1,27 @@
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from .PrivCPU import *
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from ..Tokenizer import RiscVInput
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from ..ExecutableParser import ExecutableParser
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import sys
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if __name__ == '__main__':
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files = sys.argv
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cpu = PrivCPU(RunConfig())
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try:
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loaded_exe = None
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for file in files:
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tk = cpu.get_tokenizer(RiscVInput.from_file(file))
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tk.tokenize()
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loaded_exe = cpu.load(ExecutableParser(tk).parse())
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# run the last loaded executable
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cpu.run_loaded(loaded_exe)
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except RiscemuBaseException as e:
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print("Error while parsing: {}".format(e.message()))
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import traceback
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traceback.print_exception(type(e), e, e.__traceback__)
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sys.exit(1)
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