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@ -41,7 +41,15 @@ class PrivRV32I(RV32I):
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INS_NOT_IMPLEMENTED(ins)
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def instruction_csrrwi(self, ins: 'LoadedInstruction'):
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INS_NOT_IMPLEMENTED(ins)
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ASSERT_LEN(ins.args, 3)
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rd, imm, addr = ins.get_reg(0), ins.get_imm(1), ins.get_imm(2)
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if rd != 'zero':
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self.cpu.csr.assert_can_read(self.cpu.mode, addr)
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old_val = self.cpu.csr.get(addr)
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self.regs.set(rd, old_val)
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self.cpu.csr.assert_can_write(self.cpu.mode, addr)
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self.cpu.csr.set(addr, imm)
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def instruction_csrrci(self, ins: 'LoadedInstruction'):
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INS_NOT_IMPLEMENTED(ins)
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