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[PrivRV32I] added half od csrrs instruction (reading only)

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This commit is contained in:
Anton Lydike 2021-06-08 00:21:05 +02:00
parent 052ad56310
commit 5b2b12507d
1 changed files with 9 additions and 1 deletions
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10
riscemu/priv/PrivRV32I.py
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@ -32,7 +32,15 @@ class PrivRV32I(RV32I):
self.cpu.csr.set(csr_addr, new_val)
def instruction_csrrs(self, ins: 'LoadedInstruction'):
INS_NOT_IMPLEMENTED(ins)
rd, rs, csr_addr = self.parse_crs_ins(ins)
if rs != 'zero':
# oh no, this should not happen!
INS_NOT_IMPLEMENTED(ins)
if rd != 'zero':
self.cpu.csr.assert_can_read(self.cpu.mode, csr_addr)
old_val = self.cpu.csr.get(csr_addr)
self.regs.set(rd, old_val)
def instruction_csrrc(self, ins: 'LoadedInstruction'):
INS_NOT_IMPLEMENTED(ins)