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added a whole lot of debugging info for privileged emulation

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This commit is contained in:
Anton Lydike 2021-09-30 20:58:44 +02:00
parent 3d4d36bfe4
commit d0c5abe845
2 changed files with 15 additions and 5 deletions
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7
riscemu/priv/PrivCPU.py
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@ -36,7 +36,7 @@ class PrivCPU(CPU):
Reference to the control and status registers
"""
TIME_RESOLUTION_NS: int = 1000000
TIME_RESOLUTION_NS: int = 10000000
"""
controls the resolution of the time csr register (in nanoseconds)
"""
@ -162,6 +162,8 @@ class PrivCPU(CPU):
def _handle_trap(self, trap: CpuTrap):
# implement trap handling!
self.pending_traps.append(trap)
print(FMT_CPU + "Trap {} encountered at {} (0x{:x})".format(trap, self.mmu.translate_address(self.pc), self.pc) + FMT_NONE)
def step(self, verbose=True):
try:
@ -204,7 +206,7 @@ class PrivCPU(CPU):
self.csr.set_mstatus('mpp', self.mode.value)
self.csr.set_mstatus('mie', 0)
self.csr.set('mcause', trap.mcause)
self.csr.set('mepc', self.pc-self.INS_XLEN)
self.csr.set('mepc', self.pc)
self.csr.set('mtval', trap.mtval)
self.mode = trap.priv
mtvec = self.csr.get('mtvec')
@ -242,3 +244,4 @@ class PrivCPU(CPU):
def record_perf_profile(self):
self._perf_counters.append((time.perf_counter_ns(), self.cycle))

13
riscemu/priv/PrivRV32I.py
View File

@ -77,15 +77,17 @@ class PrivRV32I(RV32I):
self.cpu.mode = PrivModes(mpp)
# restore pc
mepc = self.cpu.csr.get('mepc')
self.cpu.pc = mepc
self.cpu.pc = mepc - self.cpu.INS_XLEN
sec = self.mmu.get_sec_containing(mepc)
if sec is not None:
print(FMT_CPU + "[CPU] [{}] returning to mode {} in {}".format(
print(FMT_CPU + "[CPU] [{}] returning to mode {} in {} (0x{:x})".format(
self.cpu.cycle,
PrivModes(mpp).name,
self.mmu.translate_address(mepc)
self.mmu.translate_address(mepc),
mepc
) + FMT_NONE)
self.regs.dump_reg_a()
def instruction_uret(self, ins: 'LoadedInstruction'):
raise IllegalInstructionTrap(ins)
@ -137,6 +139,11 @@ class PrivRV32I(RV32I):
ASSERT_LEN(ins.args, 2)
reg = ins.get_reg(0)
addr = ins.get_imm(1)
if reg == 'ra' and self.cpu.mode == PrivModes.USER:
print(FMT_CPU + 'Jumping to {} (0x{:x})'.format(
self.mmu.translate_address(self.pc + addr),
self.pc + addr
) + FMT_NONE)
self.regs.set(reg, self.pc)
self.pc += addr - 4