user mode emulator finally working again
Anton Lydike
3 years ago
parent
5538034f8b
commit
b396e0c5eb
@ -1,142 +1,106 @@
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"""
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RiscEmu (c) 2021 Anton Lydike
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RiscEmu (c) 2021-2022 Anton Lydike
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SPDX-License-Identifier: MIT
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This file contains the CPU logic (not the individual instruction sets). See instructions/InstructionSet.py for more info
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This file contains the CPU logic (not the individual instruction sets). See instructions/instruction_set.py for more info
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on them.
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"""
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import sys
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from typing import Tuple, List, Dict, Callable, Type
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import typing
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from typing import List, Type
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from .types import MemoryFlags
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from .syscall import SyscallInterface, get_syscall_symbols
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from .exceptions import RiscemuBaseException, LaunchDebuggerException
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import riscemu
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from .MMU import MMU
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from .config import RunConfig
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from .registers import Registers
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from .base import BinaryDataMemorySection
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from .colors import FMT_CPU, FMT_NONE
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from .debug import launch_debug_session
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from .colors import FMT_CPU, FMT_NONE, FMT_ERROR
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import riscemu
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import typing
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from .exceptions import RiscemuBaseException, LaunchDebuggerException
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from .syscall import SyscallInterface, get_syscall_symbols
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from .types import CPU
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if typing.TYPE_CHECKING:
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from . import types, LoadedExecutable, LoadedInstruction
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from .instructions.InstructionSet import InstructionSet
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from .instructions.instruction_set import InstructionSet
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class CPU:
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class UserModeCPU(CPU):
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"""
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This class represents a single CPU. It holds references to it's mmu, registers and syscall interrupt handler.
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It is initialized with a configuration and a list of instruction sets.
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"""
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INS_XLEN = 4
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def __init__(self, conf: RunConfig, instruction_sets: List[Type['riscemu.InstructionSet']]):
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def __init__(self, instruction_sets: List[Type['riscemu.InstructionSet']]):
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"""
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Creates a CPU instance.
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:param conf: An instance of the current RunConfiguration
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:param instruction_sets: A list of instruction set classes. These must inherit from the InstructionSet class
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"""
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# setup CPU states
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self.pc = 0
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self.cycle = 0
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self.exit: bool = False
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self.exit_code: int = 0
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self.conf = conf
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self.active_debug = False # if a debugging session is currently runnign
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self.stack: typing.Optional['riscemu.LoadedMemorySection'] = None
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# setup MMU, registers and syscall handlers
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self.mmu = MMU(conf)
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self.regs = Registers(conf)
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self.syscall_int = SyscallInterface()
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# load all instruction sets
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self.instruction_sets: List[riscemu.InstructionSet] = list()
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self.instructions: Dict[str, Callable[[LoadedInstruction], None]] = dict()
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for set_class in instruction_sets:
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ins_set = set_class(self)
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self.instructions.update(ins_set.load())
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self.instruction_sets.append(ins_set)
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super().__init__(MMU(), instruction_sets)
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# provide global syscall symbols if option is set
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if conf.include_scall_symbols:
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self.mmu.global_symbols.update(get_syscall_symbols())
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self.exit_code = 0
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def continue_from_debugger(self, verbose=True):
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"""
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called from the debugger to continue running
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# setup syscall interface
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self.syscall_int = SyscallInterface()
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:param verbose: If True, will print each executed instruction to STDOUT
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"""
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self._run(verbose)
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# add global syscall symbols, but don't overwrite any user-defined symbols
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syscall_symbols = get_syscall_symbols()
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syscall_symbols.update(self.mmu.global_symbols)
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self.mmu.global_symbols.update(syscall_symbols)
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def step(self):
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def step(self, verbose=False):
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"""
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Execute a single instruction, then return.
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"""
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if self.exit:
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if self.halted:
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print(FMT_CPU + "[CPU] Program exited with code {}".format(self.exit_code) + FMT_NONE)
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else:
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try:
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self.cycle += 1
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ins = self.mmu.read_ins(self.pc)
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print(FMT_CPU + " Running 0x{:08X}:{} {}".format(self.pc, FMT_NONE, ins))
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self.pc += self.INS_XLEN
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self.run_instruction(ins)
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except LaunchDebuggerException:
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print(FMT_CPU + "[CPU] Returning to debugger!" + FMT_NONE)
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except RiscemuBaseException as ex:
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self.pc -= self.INS_XLEN
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print(ex.message())
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return
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launch_debugger = False
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def _run(self, verbose=False):
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if self.pc <= 0:
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return False
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ins = None
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try:
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while not self.exit:
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self.cycle += 1
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ins = self.mmu.read_ins(self.pc)
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if verbose:
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print(FMT_CPU + " Running 0x{:08X}:{} {}".format(self.pc, FMT_NONE, ins))
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self.pc += self.INS_XLEN
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self.run_instruction(ins)
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self.cycle += 1
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ins = self.mmu.read_ins(self.pc)
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if verbose:
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print(FMT_CPU + " Running 0x{:08X}:{} {}".format(self.pc, FMT_NONE, ins))
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self.pc += self.INS_XLEN
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self.run_instruction(ins)
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except RiscemuBaseException as ex:
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if not isinstance(ex, LaunchDebuggerException):
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print(FMT_ERROR + "[CPU] excpetion caught at 0x{:08X}: {}:".format(self.pc - 1, ins) + FMT_NONE)
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if isinstance(ex, LaunchDebuggerException):
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# if the debugger is active, raise the exception to
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if self.debugger_active:
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raise ex
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print(FMT_CPU + '[CPU] Debugger launch requested!' + FMT_NONE)
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launch_debugger = True
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else:
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print(ex.message())
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self.pc -= self.INS_XLEN
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if self.active_debug:
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print(FMT_CPU + "[CPU] Returning to debugger!" + FMT_NONE)
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return
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if self.conf.debug_on_exception:
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launch_debug_session(self, self.mmu, self.regs, "Exception encountered, launching debug:")
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if self.exit:
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print()
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print(FMT_CPU + "Program exited with code {}".format(self.exit_code) + FMT_NONE)
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sys.exit(self.exit_code)
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else:
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print()
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print(FMT_CPU + "Program stopped without exiting - perhaps you stopped the debugger?" + FMT_NONE)
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def __repr__(self):
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ex.print_stacktrace()
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print(FMT_CPU + '[CPU] Halting due to exception!' + FMT_NONE)
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self.halted = True
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if launch_debugger:
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launch_debug_session(self)
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def run(self, verbose=False):
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while not self.halted:
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self.step(verbose)
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def setup_stack(self, stack_size=1024 * 4) -> bool:
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"""
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Returns a representation of the CPU and some of its state.
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Create program stack and populate stack pointer
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:param stack_size: the size of the required stack, defaults to 4Kib
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:return:
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"""
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return "{}(pc=0x{:08X}, cycle={}, exit={}, instructions={})".format(
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self.__class__.__name__,
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self.pc,
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self.cycle,
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self.exit,
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" ".join(s.name for s in self.instruction_sets)
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stack_sec = BinaryDataMemorySection(
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bytearray(stack_size),
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'.stack',
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None, # FIXME: why does a binary data memory section require a context?
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'',
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0
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)
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if not self.mmu.load_section(stack_sec, fixed_position=False):
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return False
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self.regs.set('sp', stack_sec.base + stack_sec.size)
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