user mode emulator finally working again
This commit is contained in:
Anton Lydike
parent
5538034f8b
commit
b396e0c5eb
162
riscemu/CPU.py
162
riscemu/CPU.py
@ -1,142 +1,106 @@
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"""
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RiscEmu (c) 2021 Anton Lydike
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RiscEmu (c) 2021-2022 Anton Lydike
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SPDX-License-Identifier: MIT
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This file contains the CPU logic (not the individual instruction sets). See instructions/InstructionSet.py for more info
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This file contains the CPU logic (not the individual instruction sets). See instructions/instruction_set.py for more info
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on them.
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"""
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import sys
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from typing import Tuple, List, Dict, Callable, Type
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from .types import MemoryFlags
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from .syscall import SyscallInterface, get_syscall_symbols
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from .exceptions import RiscemuBaseException, LaunchDebuggerException
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from .MMU import MMU
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from .config import RunConfig
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from .registers import Registers
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from .debug import launch_debug_session
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from .colors import FMT_CPU, FMT_NONE, FMT_ERROR
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import typing
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from typing import List, Type
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import riscemu
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import typing
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from .MMU import MMU
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from .base import BinaryDataMemorySection
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from .colors import FMT_CPU, FMT_NONE
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from .debug import launch_debug_session
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from .exceptions import RiscemuBaseException, LaunchDebuggerException
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from .syscall import SyscallInterface, get_syscall_symbols
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from .types import CPU
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if typing.TYPE_CHECKING:
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from . import types, LoadedExecutable, LoadedInstruction
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from .instructions.InstructionSet import InstructionSet
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from .instructions.instruction_set import InstructionSet
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class CPU:
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class UserModeCPU(CPU):
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"""
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This class represents a single CPU. It holds references to it's mmu, registers and syscall interrupt handler.
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It is initialized with a configuration and a list of instruction sets.
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"""
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INS_XLEN = 4
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def __init__(self, conf: RunConfig, instruction_sets: List[Type['riscemu.InstructionSet']]):
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def __init__(self, instruction_sets: List[Type['riscemu.InstructionSet']]):
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"""
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Creates a CPU instance.
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:param conf: An instance of the current RunConfiguration
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:param instruction_sets: A list of instruction set classes. These must inherit from the InstructionSet class
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"""
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# setup CPU states
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self.pc = 0
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self.cycle = 0
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self.exit: bool = False
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self.exit_code: int = 0
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self.conf = conf
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self.active_debug = False # if a debugging session is currently runnign
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super().__init__(MMU(), instruction_sets)
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self.stack: typing.Optional['riscemu.LoadedMemorySection'] = None
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self.exit_code = 0
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# setup MMU, registers and syscall handlers
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self.mmu = MMU(conf)
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self.regs = Registers(conf)
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# setup syscall interface
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self.syscall_int = SyscallInterface()
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# load all instruction sets
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self.instruction_sets: List[riscemu.InstructionSet] = list()
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self.instructions: Dict[str, Callable[[LoadedInstruction], None]] = dict()
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for set_class in instruction_sets:
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ins_set = set_class(self)
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self.instructions.update(ins_set.load())
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self.instruction_sets.append(ins_set)
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# add global syscall symbols, but don't overwrite any user-defined symbols
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syscall_symbols = get_syscall_symbols()
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syscall_symbols.update(self.mmu.global_symbols)
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self.mmu.global_symbols.update(syscall_symbols)
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# provide global syscall symbols if option is set
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if conf.include_scall_symbols:
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self.mmu.global_symbols.update(get_syscall_symbols())
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def continue_from_debugger(self, verbose=True):
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"""
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called from the debugger to continue running
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:param verbose: If True, will print each executed instruction to STDOUT
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"""
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self._run(verbose)
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def step(self):
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def step(self, verbose=False):
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"""
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Execute a single instruction, then return.
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"""
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if self.exit:
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if self.halted:
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print(FMT_CPU + "[CPU] Program exited with code {}".format(self.exit_code) + FMT_NONE)
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else:
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try:
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self.cycle += 1
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ins = self.mmu.read_ins(self.pc)
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print(FMT_CPU + " Running 0x{:08X}:{} {}".format(self.pc, FMT_NONE, ins))
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self.pc += self.INS_XLEN
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self.run_instruction(ins)
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except LaunchDebuggerException:
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print(FMT_CPU + "[CPU] Returning to debugger!" + FMT_NONE)
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except RiscemuBaseException as ex:
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self.pc -= self.INS_XLEN
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print(ex.message())
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return
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launch_debugger = False
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def _run(self, verbose=False):
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if self.pc <= 0:
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return False
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ins = None
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try:
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while not self.exit:
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self.cycle += 1
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ins = self.mmu.read_ins(self.pc)
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if verbose:
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print(FMT_CPU + " Running 0x{:08X}:{} {}".format(self.pc, FMT_NONE, ins))
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self.pc += self.INS_XLEN
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self.run_instruction(ins)
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self.cycle += 1
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ins = self.mmu.read_ins(self.pc)
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if verbose:
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print(FMT_CPU + " Running 0x{:08X}:{} {}".format(self.pc, FMT_NONE, ins))
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self.pc += self.INS_XLEN
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self.run_instruction(ins)
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except RiscemuBaseException as ex:
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if not isinstance(ex, LaunchDebuggerException):
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print(FMT_ERROR + "[CPU] excpetion caught at 0x{:08X}: {}:".format(self.pc - 1, ins) + FMT_NONE)
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if isinstance(ex, LaunchDebuggerException):
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# if the debugger is active, raise the exception to
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if self.debugger_active:
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raise ex
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print(FMT_CPU + '[CPU] Debugger launch requested!' + FMT_NONE)
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launch_debugger = True
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else:
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print(ex.message())
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self.pc -= self.INS_XLEN
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ex.print_stacktrace()
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print(FMT_CPU + '[CPU] Halting due to exception!' + FMT_NONE)
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self.halted = True
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if self.active_debug:
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print(FMT_CPU + "[CPU] Returning to debugger!" + FMT_NONE)
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return
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if self.conf.debug_on_exception:
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launch_debug_session(self, self.mmu, self.regs, "Exception encountered, launching debug:")
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if launch_debugger:
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launch_debug_session(self)
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if self.exit:
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print()
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print(FMT_CPU + "Program exited with code {}".format(self.exit_code) + FMT_NONE)
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sys.exit(self.exit_code)
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else:
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print()
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print(FMT_CPU + "Program stopped without exiting - perhaps you stopped the debugger?" + FMT_NONE)
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def run(self, verbose=False):
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while not self.halted:
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self.step(verbose)
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def __repr__(self):
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def setup_stack(self, stack_size=1024 * 4) -> bool:
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"""
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Returns a representation of the CPU and some of its state.
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Create program stack and populate stack pointer
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:param stack_size: the size of the required stack, defaults to 4Kib
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:return:
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"""
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return "{}(pc=0x{:08X}, cycle={}, exit={}, instructions={})".format(
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self.__class__.__name__,
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self.pc,
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self.cycle,
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self.exit,
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" ".join(s.name for s in self.instruction_sets)
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stack_sec = BinaryDataMemorySection(
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bytearray(stack_size),
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'.stack',
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None, # FIXME: why does a binary data memory section require a context?
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'',
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0
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)
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if not self.mmu.load_section(stack_sec, fixed_position=False):
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return False
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self.regs.set('sp', stack_sec.base + stack_sec.size)
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@ -49,9 +49,11 @@ class MMU:
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"""
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Create a new MMU
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"""
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self.programs = list()
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self.sections = list()
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self.global_symbols = dict()
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def get_sec_containing(self, addr: T_AbsoluteAddress) -> Optional[MemorySection]:
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"""
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Returns the section that contains the address addr
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@ -79,8 +81,8 @@ class MMU:
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"""
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sec = self.get_sec_containing(addr)
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if sec is None:
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print(FMT_MEM + "[MMU] Trying to read instruction form invalid region! "
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"Have you forgotten an exit syscall or ret statement?" + FMT_NONE)
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print(FMT_MEM + "[MMU] Trying to read instruction form invalid region! (read at {}) ".format(addr)
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+ "Have you forgotten an exit syscall or ret statement?" + FMT_NONE)
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raise RuntimeError("No next instruction available!")
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return sec.read_ins(addr - sec.base)
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@ -181,8 +183,7 @@ class MMU:
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at_addr = program.base
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else:
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first_guaranteed_free_address = self.sections[-1].base + self.sections[-1].size
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at_addr = align_addr(first_guaranteed_free_address, align_to)
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at_addr = align_addr(self.get_guaranteed_free_address(), align_to)
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# trigger the load event to set all addresses in the binary
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program.loaded_trigger(at_addr)
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@ -200,10 +201,35 @@ class MMU:
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# FIXME: this is pretty unclean and should probably be solved in a better way in the future
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program.context.global_symbol_dict = self.global_symbols
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def load_section(self, sec: MemorySection, fixed_position: bool = False) -> bool:
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if fixed_position:
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if self.has_continous_free_region(sec.base, sec.base + sec.size):
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self.sections.append(sec)
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self._update_state()
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else:
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print(FMT_MEM + '[MMU] Cannot place section {} at {}, space is occupied!'.format(sec, sec.base))
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return False
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else:
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at_addr = align_addr(self.get_guaranteed_free_address(), 8)
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sec.base = at_addr
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self.sections.append(sec)
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self._update_state()
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return True
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def _update_state(self):
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"""
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Called whenever a section or program is added to keep the list of programs and sections consistent
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:return:
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"""
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self.programs.sort(key=lambda bin: bin.base)
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self.sections.sort(key=lambda sec: sec.base)
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def get_guaranteed_free_address(self) -> T_AbsoluteAddress:
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if len(self.sections) == 0:
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return 0x100
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else:
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return self.sections[-1].base + self.sections[-1].size
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def __repr__(self):
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return "MMU(\n\t{}\n)".format(
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"\n\t".join(repr(x) for x in self.programs)
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@ -5,17 +5,18 @@ SPDX-License-Identifier: MIT
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This file holds the logic for starting the emulator from the CLI
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"""
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from riscemu.CPU import UserModeCPU
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if __name__ == '__main__':
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from . import *
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from .config import RunConfig
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from .helpers import *
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from .instructions import InstructionSetDict
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from riscemu.parser import AssemblyFileLoader
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import argparse
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import sys
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all_ins_names = list(InstructionSetDict.keys())
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class OptionStringAction(argparse.Action):
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def __init__(self, option_strings, dest, keys=None, omit_empty=False, **kwargs):
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if keys is None:
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@ -93,17 +94,21 @@ if __name__ == '__main__':
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]
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try:
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cpu = CPU(cfg, ins_to_load)
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loaded_exe = None
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for file in args.files:
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tk = cpu.get_tokenizer(RiscVInput.from_file(file))
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tk.tokenize()
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loaded_exe = cpu.load(ExecutableParser(tk).parse())
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# run the last loaded executable
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cpu.run_loaded(loaded_exe)
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except RiscemuBaseException as e:
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print("Error while parsing: {}".format(e.message()))
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import traceback
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cpu = UserModeCPU(ins_to_load)
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opts = AssemblyFileLoader.get_options(sys.argv)
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for file in args.files:
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loader = AssemblyFileLoader.instantiate(file, opts)
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cpu.load_program(loader.parse())
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# run the last loaded executable
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cpu.setup_stack(cfg.stack_size)
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# launch the last loaded program
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cpu.launch(cpu.mmu.programs[-1])
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except RiscemuBaseException as e:
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print("Error: {}".format(e.message()))
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e.print_stacktrace()
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traceback.print_exception(type(e), e, e.__traceback__)
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sys.exit(1)
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@ -1,11 +1,10 @@
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"""
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RiscEmu (c) 2021 Anton Lydike
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RiscEmu (c) 2021-2022 Anton Lydike
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SPDX-License-Identifier: MIT
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"""
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from dataclasses import dataclass
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from typing import Optional
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@dataclass(frozen=True, init=True)
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@ -4,35 +4,33 @@ RiscEmu (c) 2021 Anton Lydike
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SPDX-License-Identifier: MIT
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"""
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import typing
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from .registers import Registers
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from .colors import FMT_DEBUG, FMT_NONE
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from .types import Instruction
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from .base import SimpleInstruction
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from .helpers import *
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if typing.TYPE_CHECKING:
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from . import *
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from riscemu import CPU, Registers
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def launch_debug_session(cpu: 'CPU', mmu: 'MMU', reg: 'Registers', prompt=""):
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if not cpu.conf.debug_instruction or cpu.active_debug:
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def launch_debug_session(cpu: 'CPU', prompt=""):
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if cpu.debugger_active:
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return
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import code
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import readline
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import rlcompleter
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cpu.active_debug = True
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# set the active debug flag
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cpu.debugger_active = True
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# setup some aliases:
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registers = reg
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regs = reg
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memory = mmu
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mem = mmu
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syscall_interface = cpu.syscall_int
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registers = cpu.regs
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regs = cpu.regs
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memory = cpu.mmu
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mem = cpu.mmu
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mmu = cpu.mmu
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# setup helper functions:
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def dump(what, *args, **kwargs):
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if isinstance(what, Registers):
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if what == regs:
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regs.dump(*args, **kwargs)
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else:
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mmu.dump(what, *args, **kwargs)
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@ -50,20 +48,39 @@ def launch_debug_session(cpu: 'CPU', mmu: 'MMU', reg: 'Registers', prompt=""):
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return
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bin = mmu.get_bin_containing(cpu.pc)
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ins = Instruction(name, list(args), bin)
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print(FMT_DEBUG + "Running instruction " + ins + FMT_NONE)
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ins = SimpleInstruction(
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name,
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tuple(args),
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bin.context,
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cpu.pc)
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print(FMT_DEBUG + "Running instruction {}".format(ins) + FMT_NONE)
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cpu.run_instruction(ins)
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def cont(verbose=False):
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cpu.continue_from_debugger(verbose)
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try:
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cpu.run(verbose)
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except LaunchDebuggerException:
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print(FMT_DEBUG + 'Returning to debugger...')
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return
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def step():
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cpu.step()
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try:
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cpu.step()
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except LaunchDebuggerException:
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return
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# collect all variables
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sess_vars = globals()
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sess_vars.update(locals())
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# add tab completion
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readline.set_completer(rlcompleter.Completer(sess_vars).complete)
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readline.parse_and_bind("tab: complete")
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code.InteractiveConsole(sess_vars).interact(banner=FMT_DEBUG + prompt + FMT_NONE, exitmsg="Exiting debugger")
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cpu.active_debug = False
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relaunch_debugger = False
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try:
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code.InteractiveConsole(sess_vars).interact(banner=FMT_DEBUG + prompt + FMT_NONE, exitmsg="Exiting debugger")
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finally:
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cpu.debugger_active = False
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@ -17,6 +17,9 @@ class RiscemuBaseException(BaseException):
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def message(self):
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pass
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def print_stacktrace(self):
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import traceback
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traceback.print_exception(type(self), self, self.__traceback__)
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# Parsing exceptions:
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@ -115,13 +118,15 @@ class InvalidAllocationException(RiscemuBaseException):
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class UnimplementedInstruction(RiscemuBaseException):
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def __init__(self, ins: 'Instruction'):
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def __init__(self, ins: 'Instruction', context = None):
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self.ins = ins
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self.context = context
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def message(self):
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return FMT_CPU + "{}({})".format(
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return FMT_CPU + "{}({}{})".format(
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self.__class__.__name__,
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repr(self.ins)
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repr(self.ins),
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', context={}'.format(self.context) if self.context is not None else ''
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) + FMT_NONE
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@ -1,4 +1,4 @@
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from .InstructionSet import InstructionSet, Instruction
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from .instruction_set import InstructionSet, Instruction
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from ..exceptions import INS_NOT_IMPLEMENTED
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from ..helpers import int_from_bytes, int_to_bytes, to_unsigned, to_signed
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@ -4,7 +4,8 @@ RiscEmu (c) 2021 Anton Lydike
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SPDX-License-Identifier: MIT
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"""
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|
||||
from .InstructionSet import *
|
||||
from .instruction_set import *
|
||||
from ..CPU import UserModeCPU
|
||||
|
||||
from ..helpers import int_from_bytes, int_to_bytes, to_unsigned, to_signed
|
||||
from ..colors import FMT_DEBUG, FMT_NONE
|
||||
@ -116,14 +117,8 @@ class RV32I(InstructionSet):
|
||||
)
|
||||
|
||||
def instruction_add(self, ins: 'Instruction'):
|
||||
dst = ""
|
||||
if self.cpu.conf.add_accept_imm:
|
||||
try:
|
||||
dst, rs1, rs2 = self.parse_rd_rs_imm(ins)
|
||||
except:
|
||||
pass
|
||||
if not dst:
|
||||
dst, rs1, rs2 = self.parse_rd_rs_rs(ins)
|
||||
# FIXME: once configuration is figured out, add flag to support immediate arg in add instruction
|
||||
dst, rs1, rs2 = self.parse_rd_rs_rs(ins)
|
||||
|
||||
self.regs.set(
|
||||
dst,
|
||||
@ -292,20 +287,19 @@ class RV32I(InstructionSet):
|
||||
|
||||
def instruction_scall(self, ins: 'Instruction'):
|
||||
ASSERT_LEN(ins.args, 0)
|
||||
|
||||
if not isinstance(self.cpu, UserModeCPU):
|
||||
# FIXME: add exception for syscall not supported or something
|
||||
raise
|
||||
|
||||
syscall = Syscall(self.regs.get('a7'), self.cpu)
|
||||
self.cpu.syscall_int.handle_syscall(syscall)
|
||||
|
||||
def instruction_sbreak(self, ins: 'Instruction'):
|
||||
ASSERT_LEN(ins.args, 0)
|
||||
if self.cpu.active_debug:
|
||||
print(FMT_DEBUG + "Debug instruction encountered at 0x{:08X}".format(self.pc - 1) + FMT_NONE)
|
||||
raise LaunchDebuggerException()
|
||||
launch_debug_session(
|
||||
self.cpu,
|
||||
self.mmu,
|
||||
self.regs,
|
||||
"Debug instruction encountered at 0x{:08X}".format(self.pc - 1)
|
||||
)
|
||||
|
||||
print(FMT_DEBUG + "Debug instruction encountered at 0x{:08X}".format(self.pc - 1) + FMT_NONE)
|
||||
raise LaunchDebuggerException()
|
||||
|
||||
def instruction_nop(self, ins: 'Instruction'):
|
||||
ASSERT_LEN(ins.args, 0)
|
||||
|
||||
@ -4,7 +4,7 @@ RiscEmu (c) 2021 Anton Lydike
|
||||
SPDX-License-Identifier: MIT
|
||||
"""
|
||||
|
||||
from .InstructionSet import *
|
||||
from .instruction_set import *
|
||||
from ..exceptions import INS_NOT_IMPLEMENTED
|
||||
|
||||
|
||||
|
||||
@ -6,7 +6,7 @@ SPDX-License-Identifier: MIT
|
||||
This package holds all instruction sets, available to the processor
|
||||
"""
|
||||
|
||||
from .InstructionSet import InstructionSet
|
||||
from .instruction_set import InstructionSet
|
||||
from .RV32M import RV32M
|
||||
from .RV32I import RV32I
|
||||
from .RV32A import RV32A
|
||||
|
||||
@ -53,6 +53,7 @@ def parse_tokens(name: str, tokens_iter: Iterable[Token]) -> Program:
|
||||
for token, args in composite_tokenizer(Peekable[Token](tokens_iter)):
|
||||
if token.type not in PARSERS:
|
||||
raise ParseException("Unexpected token type: {}, {}".format(token, args))
|
||||
print('{}: {}'.format(token, args))
|
||||
PARSERS[token.type](token, args, context)
|
||||
|
||||
return context.finalize()
|
||||
@ -73,6 +74,8 @@ def composite_tokenizer(tokens_iter: Iterable[Token]) -> Iterable[Tuple[Token, T
|
||||
token = next(tokens)
|
||||
if token.type in (TokenType.PSEUDO_OP, TokenType.LABEL, TokenType.INSTRUCTION_NAME):
|
||||
yield token, tuple(take_arguments(tokens))
|
||||
else:
|
||||
print("skipped {}".format(token))
|
||||
|
||||
|
||||
def take_arguments(tokens: Peekable[Token]) -> Iterable[str]:
|
||||
@ -85,12 +88,14 @@ def take_arguments(tokens: Peekable[Token]) -> Iterable[str]:
|
||||
while True:
|
||||
if tokens.peek().type == TokenType.ARGUMENT:
|
||||
yield next(tokens).value
|
||||
if tokens.peek().type == TokenType.COMMA:
|
||||
next(tokens)
|
||||
elif tokens.peek().type == TokenType.NEWLINE:
|
||||
next(tokens)
|
||||
break
|
||||
break
|
||||
elif tokens.peek().type == TokenType.COMMA:
|
||||
next(tokens)
|
||||
else:
|
||||
break
|
||||
|
||||
# raise ParseException("Expected newline, instead got {}".format(tokens.peek()))
|
||||
|
||||
|
||||
|
||||
@ -16,7 +16,7 @@ from ..instructions import RV32A, RV32M
|
||||
|
||||
if typing.TYPE_CHECKING:
|
||||
from riscemu import types, LoadedExecutable, LoadedInstruction
|
||||
from riscemu.instructions.InstructionSet import InstructionSet
|
||||
from riscemu.instructions.instruction_set import InstructionSet
|
||||
|
||||
|
||||
class PrivCPU(CPU):
|
||||
@ -83,7 +83,7 @@ class PrivCPU(CPU):
|
||||
self.launch_debug = False
|
||||
launch_debug_session(self, self.mmu, self.regs,
|
||||
"Launching debugger:")
|
||||
if not self.active_debug:
|
||||
if not self.debugger_active:
|
||||
self._run(verbose)
|
||||
else:
|
||||
print()
|
||||
|
||||
@ -1,28 +1,23 @@
|
||||
"""
|
||||
RiscEmu (c) 2021 Anton Lydike
|
||||
RiscEmu (c) 2021-2022 Anton Lydike
|
||||
|
||||
SPDX-License-Identifier: MIT
|
||||
"""
|
||||
|
||||
from .config import RunConfig
|
||||
from .helpers import *
|
||||
from collections import defaultdict
|
||||
from .exceptions import InvalidRegisterException
|
||||
|
||||
from .helpers import *
|
||||
|
||||
|
||||
class Registers:
|
||||
"""
|
||||
Represents a bunch of registers
|
||||
"""
|
||||
|
||||
def __init__(self, conf: RunConfig):
|
||||
"""
|
||||
Initialize the register configuration, respecting the RunConfig conf
|
||||
:param conf: The RunConfig
|
||||
"""
|
||||
def __init__(self):
|
||||
self.vals = defaultdict(lambda: 0)
|
||||
self.last_set = None
|
||||
self.last_read = None
|
||||
self.conf = conf
|
||||
|
||||
def dump(self, full=False):
|
||||
"""
|
||||
@ -96,7 +91,7 @@ class Registers:
|
||||
"""
|
||||
if reg == 'zero':
|
||||
return False
|
||||
#if reg not in Registers.all_registers():
|
||||
# if reg not in Registers.all_registers():
|
||||
# raise InvalidRegisterException(reg)
|
||||
# replace fp register with s1, as these are the same register
|
||||
if reg == 'fp':
|
||||
@ -114,7 +109,7 @@ class Registers:
|
||||
:param mark_read: If the register should be markes as "last read" (only used internally)
|
||||
:return: The contents of register reg
|
||||
"""
|
||||
#if reg not in Registers.all_registers():
|
||||
# if reg not in Registers.all_registers():
|
||||
# raise InvalidRegisterException(reg)
|
||||
if reg == 'fp':
|
||||
reg = 's0'
|
||||
|
||||
@ -15,7 +15,7 @@ import riscemu
|
||||
import typing
|
||||
|
||||
if typing.TYPE_CHECKING:
|
||||
from . import CPU
|
||||
from riscemu.CPU import UserModeCPU
|
||||
|
||||
SYSCALLS = {
|
||||
63: 'read',
|
||||
@ -43,7 +43,7 @@ class Syscall:
|
||||
"""
|
||||
id: int
|
||||
"""The syscall number (e.g. 64 - write)"""
|
||||
cpu: 'riscemu.CPU'
|
||||
cpu: 'UserModeCPU'
|
||||
"""The CPU object that created the syscall"""
|
||||
|
||||
@property
|
||||
@ -146,7 +146,8 @@ class SyscallInterface:
|
||||
|
||||
Requires running with flag scall-fs
|
||||
"""
|
||||
if not scall.cpu.conf.scall_fs:
|
||||
# FIXME: this should be toggleable in a global setting or somethign
|
||||
if True:
|
||||
print(FMT_SYSCALL + '[Syscall] open: opening files not supported without scall-fs flag!' + FMT_NONE)
|
||||
return scall.ret(-1)
|
||||
|
||||
@ -193,7 +194,7 @@ class SyscallInterface:
|
||||
"""
|
||||
Exit syscall. Exits the system with status code a0
|
||||
"""
|
||||
scall.cpu.exit = True
|
||||
scall.cpu.halted = True
|
||||
scall.cpu.exit_code = scall.cpu.regs.get('a0')
|
||||
|
||||
def __repr__(self):
|
||||
|
||||
@ -14,7 +14,7 @@ from .exceptions import ParseException
|
||||
|
||||
LINE_COMMENT_STARTERS = ('#', ';', '//')
|
||||
WHITESPACE_PATTERN = re.compile(r'\s+')
|
||||
MEMORY_ADDRESS_PATTERN = re.compile(r'^(0[xX][A-f0-9]+|\d+|0b[0-1]+)\(([A-z]+[0-9]{0,2})\)$')
|
||||
MEMORY_ADDRESS_PATTERN = re.compile(r'^(0[xX][A-f0-9]+|\d+|0b[0-1]+|[A-z0-9_-]+)\(([A-z]+[0-9]{0,2})\)$')
|
||||
REGISTER_NAMES = RISCV_REGS
|
||||
|
||||
|
||||
|
||||
@ -9,16 +9,20 @@ See base.py for some basic implementations of these classes
|
||||
"""
|
||||
import os
|
||||
import re
|
||||
import typing
|
||||
from abc import ABC, abstractmethod
|
||||
from collections import defaultdict
|
||||
from dataclasses import dataclass
|
||||
from typing import Dict, List, Optional, Tuple, Set, Union, Generator, Iterator, Callable, Type
|
||||
from typing import Dict, List, Optional, Tuple, Set, Union, Iterator, Callable, Type
|
||||
|
||||
from . import MMU, InstructionSet
|
||||
from .assembler import get_section_base_name
|
||||
from .colors import FMT_MEM, FMT_NONE, FMT_UNDERLINE, FMT_ORANGE, FMT_PARSE, FMT_RED, FMT_BOLD
|
||||
from .colors import FMT_MEM, FMT_NONE, FMT_UNDERLINE, FMT_ORANGE, FMT_RED, FMT_BOLD
|
||||
from .exceptions import ParseException
|
||||
from .helpers import format_bytes
|
||||
from .helpers import format_bytes, get_section_base_name
|
||||
from .registers import Registers
|
||||
|
||||
if typing.TYPE_CHECKING:
|
||||
from .MMU import MMU
|
||||
from .instructions.instruction_set import InstructionSet
|
||||
|
||||
# define some base type aliases so we can keep track of absolute and relative addresses
|
||||
T_RelativeAddress = int
|
||||
@ -231,7 +235,7 @@ class Program:
|
||||
self.sections = []
|
||||
self.global_labels = set()
|
||||
self.base = base
|
||||
self.loaded = False
|
||||
self.is_loaded = False
|
||||
|
||||
def add_section(self, sec: MemorySection):
|
||||
# print a warning when a section is located before the programs base
|
||||
@ -286,7 +290,7 @@ class Program:
|
||||
for sec in self.sections:
|
||||
sec.base += at_addr
|
||||
|
||||
if self.base != at_addr:
|
||||
if self.base is not None and self.base != at_addr:
|
||||
# move sections so they are located where they want to be located
|
||||
offset = at_addr - self.base
|
||||
for sec in self.sections:
|
||||
@ -354,7 +358,8 @@ class CPU(ABC):
|
||||
INS_XLEN: int = 4
|
||||
|
||||
# housekeeping variables
|
||||
mmu: MMU
|
||||
regs: Registers
|
||||
mmu: 'MMU'
|
||||
pc: T_AbsoluteAddress
|
||||
cycle: int
|
||||
halted: bool
|
||||
@ -364,10 +369,11 @@ class CPU(ABC):
|
||||
|
||||
# instruction information
|
||||
instructions: Dict[str, Callable[[Instruction], None]]
|
||||
instruction_sets: Set[InstructionSet]
|
||||
instruction_sets: Set['InstructionSet']
|
||||
|
||||
def __init__(self, mmu: MMU, instruction_sets: List[Type[InstructionSet]]):
|
||||
def __init__(self, mmu: 'MMU', instruction_sets: List[Type['InstructionSet']]):
|
||||
self.mmu = mmu
|
||||
self.regs = Registers()
|
||||
|
||||
self.instruction_sets = set()
|
||||
self.instructions = dict()
|
||||
@ -377,6 +383,7 @@ class CPU(ABC):
|
||||
self.instructions.update(ins_set.load())
|
||||
self.instruction_sets.add(ins_set)
|
||||
|
||||
self.halted = False
|
||||
self.cycle = 0
|
||||
self.pc = 0
|
||||
self.debugger_active = False
|
||||
@ -410,3 +417,19 @@ class CPU(ABC):
|
||||
self.halted,
|
||||
" ".join(s.name for s in self.instruction_sets)
|
||||
)
|
||||
|
||||
@abstractmethod
|
||||
def step(self, verbose=False):
|
||||
pass
|
||||
|
||||
@abstractmethod
|
||||
def run(self, verbose=False):
|
||||
pass
|
||||
|
||||
def launch(self, program: Program, verbose: bool = False):
|
||||
if program not in self.mmu.programs:
|
||||
print(FMT_RED + '[CPU] Cannot launch program that\'s not loaded!' + FMT_NONE)
|
||||
return
|
||||
|
||||
self.pc = program.entrypoint
|
||||
self.run(verbose)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user