[Regsietrs] ensuring register values are 32bit

2021-06-08 11:36:00 +02:00 · 2021-06-08 11:36:00 +02:00 · c7b3693740
commit c7b3693740
parent cc598c0910
1 changed files with 1 additions and 1 deletions
--- a/riscemu/Registers.py
+++ b/riscemu/Registers.py
@ -103,7 +103,7 @@ class Registers:
            reg = 's1'
        if mark_set:
            self.last_set = reg
-        self.vals[reg] = val
+        self.vals[reg] = val & (2**32 - 1)
        return True

    def get(self, reg, mark_read=True):