[PrivCPU, PrivRV32I] fix for relative jumps and branches
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@ -68,8 +68,8 @@ class PrivCPU(CPU):
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ins = self.mmu.read_ins(self.pc)
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if verbose:
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print(FMT_CPU + " Running 0x{:08X}:{} {}".format(self.pc, FMT_NONE, ins))
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self.pc += self.INS_XLEN
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self.run_instruction(ins)
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self.pc += self.INS_XLEN
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except CpuTrap as trap:
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mie = self.csr.get_mstatus('mie')
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if not mie:
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@ -76,12 +76,12 @@ class PrivRV32I(RV32I):
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def instruction_beq(self, ins: 'LoadedInstruction'):
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rs1, rs2, dst = self.parse_rs_rs_imm(ins)
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if rs1 == rs2:
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self.pc += dst
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self.pc += dst - 4
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def instruction_bne(self, ins: 'LoadedInstruction'):
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rs1, rs2, dst = self.parse_rs_rs_imm(ins)
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if rs1 != rs2:
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self.pc += dst
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self.pc += dst - 4
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def instruction_blt(self, ins: 'LoadedInstruction'):
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rs1, rs2, dst = self.parse_rs_rs_imm(ins)
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@ -91,17 +91,17 @@ class PrivRV32I(RV32I):
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def instruction_bge(self, ins: 'LoadedInstruction'):
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rs1, rs2, dst = self.parse_rs_rs_imm(ins)
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if rs1 >= rs2:
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self.pc += dst
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self.pc += dst - 4
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def instruction_bltu(self, ins: 'LoadedInstruction'):
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rs1, rs2, dst = self.parse_rs_rs_imm(ins, signed=False)
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if rs1 < rs2:
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self.pc += dst
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self.pc += dst - 4
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def instruction_bgeu(self, ins: 'LoadedInstruction'):
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rs1, rs2, dst = self.parse_rs_rs_imm(ins, signed=False)
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if rs1 >= rs2:
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self.pc += dst
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self.pc += dst - 4
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# technically deprecated
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def instruction_j(self, ins: 'LoadedInstruction'):
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@ -112,13 +112,13 @@ class PrivRV32I(RV32I):
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reg = ins.get_reg(0)
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addr = ins.get_imm(1)
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self.regs.set(reg, self.pc)
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self.pc += addr
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self.pc += addr - 4
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def instruction_jalr(self, ins: 'LoadedInstruction'):
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ASSERT_LEN(ins.args, 3)
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rd, rs, imm = self.parse_rd_rs_imm(ins)
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self.regs.set(rd, self.pc)
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self.pc = rs + imm
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self.pc = rs + imm - 4
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def parse_crs_ins(self, ins: 'LoadedInstruction'):
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ASSERT_LEN(ins.args, 3)
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