made sure register values adhere to correct 32bit two's complement standard - fixes #4

riscemu/Registers.py

@@ -104,11 +104,7 @@ class Registers:
         if mark_set:
             self.last_set = reg
         # check 32 bit signed bounds
-        if val < -2147483648:
-            val = -2147483648
-        elif val > 2147483647:
-            val = 2147483647
-        self.vals[reg] = val
+        self.vals[reg] = bind_twos_complement(val)
         return True
 
     def get(self, reg, mark_read=True):

riscemu/helpers.py

@@ -92,3 +92,16 @@ def format_bytes(byte_arr: bytearray, fmt: str, group: int = 1, highlight: int =
                                  highlight)
     if fmt == 'ascii':
         return "".join(repr(chr(b))[1:-1] for b in byte_arr)
+
+
+def bind_twos_complement(val):
+    """
+    does over/underflows for 32 bit two's complement numbers
+    :param val:
+    :return:
+    """
+    if val < -2147483648:
+        return val + 4294967296
+    elif val > 2147483647:
+        return val - 4294967296
+    return val