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[CPU] set correct MISA

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This commit is contained in:
Anton Lydike 2021-05-25 11:14:52 +02:00
parent a1f29b9d97
commit 6653ef7e7c
1 changed files with 3 additions and 3 deletions
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6
riscemu/priv/PrivCPU.py
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@ -131,11 +131,11 @@ class PrivCPU(CPU):
def _init_csr(self):
# set up CSR
self.csr = CSR()
# TODO: Actually populate the CSR with real data (vendorID, heartID, machine implementation etc)
self.csr.set('mhartid', 0) # core id
# TODO: set correct value
self.csr.set('mimpid', 1) # implementation id
# TODO: set correct misa
self.csr.set('misa', 1) # available ISA
# set mxl to 1 (32 bit) and set bits for i and m isa
self.csr.set('misa', (1 << 30) + (1 << 8) + (1 << 12)) # available ISA
@self.csr.callback('halt')
def halt(old: int, new: int):