code cleanup to increase visibility

This commit is contained in:
Anton Lydike 2021-09-30 22:04:49 +02:00
parent d09b7a5cb1
commit 7ab3f8361d
3 changed files with 11 additions and 15 deletions

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@ -26,5 +26,5 @@ from .CPU import CPU
from .Config import RunConfig
__author__ = "Anton Lydike <Anton@Lydike.com"
__author__ = "Anton Lydike <Anton@Lydike.com>"
__copyright__ = "Copyright 2021 Anton Lydike"

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@ -2,21 +2,20 @@
Laods a memory image with debug information into memory
"""
import json
from functools import lru_cache
from typing import Dict, List, Optional, TYPE_CHECKING
from .ElfLoader import ElfInstruction, ElfLoadedMemorySection, InstructionAccessFault, InstructionAddressMisalignedTrap
from .PrivMMU import PrivMMU
from ..Config import RunConfig
from ..Executable import Executable, LoadedExecutable, LoadedMemorySection, LoadedInstruction, MemoryFlags
from .ElfLoader import ElfInstruction, ElfLoadedMemorySection, InstructionAccessFault, InstructionAddressMisalignedTrap
from ..decoder import decode
from ..Executable import LoadedMemorySection, MemoryFlags
from ..IO.IOModule import IOModule
from .privmodes import PrivModes
from ..colors import FMT_ERROR, FMT_NONE, FMT_MEM
import json
from functools import lru_cache
from typing import Dict, List, Tuple, Optional, TYPE_CHECKING
from ..decoder import decode
if TYPE_CHECKING:
from .PrivCPU import PrivCPU
pass
class MemoryImageMMU(PrivMMU):

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@ -7,15 +7,12 @@ import time
from riscemu.CPU import *
from .CSR import CSR
from .ElfLoader import ElfExecutable
from .ImageLoader import MemoryImageMMU
from .Exceptions import *
from .PrivMMU import PrivMMU
from ..IO import TextIO
from .PrivRV32I import PrivRV32I
from .privmodes import PrivModes
from ..IO import TextIO
from ..instructions import RV32A, RV32M
import json
if typing.TYPE_CHECKING:
from riscemu import Executable, LoadedExecutable, LoadedInstruction
@ -195,7 +192,7 @@ class PrivCPU(CPU):
# select best interrupt
# TODO: actually select based on the official ranking
trap = self.pending_traps.pop() # use the most recent trap
if not isinstance(trap, TimerInterrupt) or True:
if self.conf.verbosity > 0:
print(FMT_CPU + "[CPU] taking trap {}!".format(trap) + FMT_NONE)
if trap.priv != PrivModes.MACHINE: