[CpuTraps] fixed formatting for mcause registers

3 years ago · baa1f24eb7
parent 777717ed2e
commit baa1f24eb7
1 changed files with 1 additions and 1 deletions
--- a/riscemu/priv/Exceptions.py
+++ b/riscemu/priv/Exceptions.py
@ -50,7 +50,7 @@ class CpuTrap(BaseException):

    @property
    def mcause(self):
-        return (self.code << 31) + self.interrupt
+        return (self.interrupt << 31) + self.code

    def __repr__(self):
        name = "Reserved interrupt({}, {})".format(self.interrupt, self.code)