fixed priv start code, added tests
Anton Lydike
3 years ago
parent
4f1c73df9e
commit
cd5795bb74
@ -0,0 +1,73 @@
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import contextlib
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import os
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from abc import abstractmethod
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from tempfile import NamedTemporaryFile
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from typing import Optional, Union, Tuple
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from unittest import TestCase
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from riscemu import CPU, UserModeCPU, InstructionSetDict, RunConfig
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from riscemu.types import Program
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class EndToEndTest(TestCase):
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def __init__(self, cpu: Optional[CPU] = None):
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super().__init__()
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if cpu is None:
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cpu = UserModeCPU(InstructionSetDict.values(), RunConfig())
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self.cpu = cpu
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@abstractmethod
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def get_source(self) -> Tuple[str, Union[bytes, str, bytearray]]:
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"""
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This method returns the source code of the program
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:return:
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"""
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pass
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def test_run_program(self):
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"""
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Runs the program and verifies output
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:return:
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"""
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with self.with_source_file() as names:
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fname, orig_name = names
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loader = self.cpu.get_best_loader_for(fname)
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self.program = loader.instantiate(fname, loader.get_options([])).parse()
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self._change_program_file_name(self.program, orig_name)
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self.cpu.load_program(self.program)
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self.after_program_load(self.program)
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if isinstance(self.cpu, UserModeCPU):
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self.cpu.setup_stack()
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try:
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self.cpu.launch(self.program)
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except Exception as ex:
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if self.is_exception_expected(ex):
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pass
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raise ex
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@contextlib.contextmanager
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def with_source_file(self):
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name, content = self.get_source()
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if isinstance(content, str):
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f = NamedTemporaryFile('w', suffix=name, delete=False)
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else:
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f = NamedTemporaryFile('wb', suffix=name, delete=False)
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f.write(content)
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f.flush()
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f.close()
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try:
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yield f.name, name
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finally:
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os.unlink(f.name)
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def after_program_load(self, program):
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pass
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def is_exception_expected(self, ex: Exception) -> bool:
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return False
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def _change_program_file_name(self, program: Program, new_name: str):
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program.name = new_name
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for sec in program.sections:
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sec.owner = new_name
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@ -0,0 +1,77 @@
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from riscemu.colors import FMT_ERROR, FMT_NONE, FMT_BOLD, FMT_GREEN
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from riscemu.exceptions import ASSERT_LEN
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from riscemu.helpers import int_from_bytes
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from riscemu.instructions import InstructionSet
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from riscemu.types import Instruction, CPU
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from riscemu.decoder import RISCV_REGS
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FMT_SUCCESS = FMT_GREEN + FMT_BOLD
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def assert_equals(ins: Instruction, cpu: CPU):
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a, b = (get_arg_from_ins(ins, i, cpu) for i in (0, 2))
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return a == b
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def assert_equals_mem(ins: Instruction, cpu: CPU):
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a, b = (get_arg_from_ins(ins, i, cpu) for i in (0, 2))
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a = cpu.mmu.read_int(a)
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return a == b
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def assert_in(ins: Instruction, cpu: CPU):
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a = get_arg_from_ins(ins, 0, cpu)
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others = [get_arg_from_ins(ins, i, cpu) for i in range(2, len(ins.args))]
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return a in others
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def _not(func):
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def test(ins: Instruction, cpu: CPU):
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return not func(ins, cpu)
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return test
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def get_arg_from_ins(ins: Instruction, num: int, cpu: CPU):
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a = ins.args[num]
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if a in RISCV_REGS:
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return cpu.regs.get(a)
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return ins.get_imm(num)
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assert_ops = {
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'==': assert_equals,
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'!=': _not(assert_equals),
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'in': assert_in,
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'not_in': _not(assert_in),
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}
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class TestIS(InstructionSet):
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def __init__(self, cpu: 'CPU'):
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print('[Test] loading testing ISA, this is only meant for running testcases and is not part of the RISC-V ISA!')
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self.failed = False
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super().__init__(cpu)
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def instruction_assert(self, ins: Instruction):
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if len(ins.args) < 3:
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print(FMT_ERROR + '[Test] Unknown assert statement: {}'.format(ins) + FMT_NONE)
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return
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op = ins.args[1]
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if op not in assert_ops:
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print(FMT_ERROR + '[Test] Unknown operation statement: {} in {}'.format(op, ins) + FMT_NONE)
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return
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if assert_ops[op](ins, self.cpu):
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print(FMT_SUCCESS + '[TestCase] 🟢 passed assertion {}'.format(ins))
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else:
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print(FMT_ERROR + '[TestCase] 🔴 failed assertion {}'.format(ins))
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self.cpu.halted = True
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self.failed = True
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def instruction_fail(self, ins: Instruction):
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print(FMT_ERROR + '[TestCase] 🔴 reached fail instruction! {}'.format(ins))
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self.cpu.halted = True
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self.failed = True
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def assert_mem(self, ins: Instruction):
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@ -0,0 +1,53 @@
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from riscemu import AssemblyFileLoader
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from riscemu.colors import *
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FMT_SUCCESS = FMT_GREEN + FMT_BOLD
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def run_test(path: str):
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from riscemu import CPU, UserModeCPU, RunConfig
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from riscemu.instructions import InstructionSetDict
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from test.test_isa import TestIS
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import os
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fname = os.path.basename(path)
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ISAs = list(InstructionSetDict.values())
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ISAs.append(TestIS)
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cpu = UserModeCPU(ISAs, RunConfig())
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try:
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program = AssemblyFileLoader(path, {}).parse()
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cpu.load_program(program)
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cpu.launch(program)
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except Exception as ex:
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print(FMT_ERROR + '[Test] 🔴 failed with exception "{}" ({})'.format(ex, fname) + FMT_NONE)
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raise ex
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if cpu.halted:
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for isa in cpu.instruction_sets:
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if isinstance(isa, TestIS):
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if not isa.failed:
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print(FMT_SUCCESS + '[Test] 🟢 successful {}'.format(fname) + FMT_NONE)
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return not isa.failed
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return False
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if __name__ == '__main__':
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import os
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import glob
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successes = 0
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failures = 0
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ttl = 0
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for path in glob.glob(f'{os.path.dirname(__file__)}/*.asm'):
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print(FMT_BLUE + '[Test] running testcase ' + os.path.basename(path) + FMT_NONE)
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ttl += 1
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if run_test(path):
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successes += 1
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else:
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failures += 1
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@ -0,0 +1,7 @@
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.data
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data:
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.word 0xFFFFFFFF, 0x0000FFFF, 0xFF00FF00, 0x7FFFFFFF
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.text
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ebreak
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@ -0,0 +1,20 @@
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.text
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main:
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addi a0, zero, main
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addi a1, zero, main
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addi t0, zero, 1000
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assert a0, ==, 0x100
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1:
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addi a1, a1, 1
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blt a1, t0, 1b
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sub a1, a1, a0
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j 1f
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addi a1, zero, 0
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fail
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1:
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assert a1, ==, 744
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add a0, zero, a1 ; set exit code to a1
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addi a7, zero, SCALL_EXIT ; exit syscall code
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scall
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fail
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