Anton Lydike
|
dc4dca6fea
|
[wip] almost done with the rework of the parser and internal data structure representation of programs
|
2021-12-18 00:25:39 +01:00 |
|
Anton Lydike
|
84562de98f
|
added tests for tokenizer
|
2021-12-14 07:33:17 +01:00 |
|
Anton Lydike
|
d5a4acef67
|
tokenizer reimplemented
|
2021-12-13 23:23:55 +01:00 |
|
Anton Lydike
|
52e189c226
|
fixed missing newline at the end of the file
|
2021-12-10 13:46:57 +01:00 |
|
Anton Lydike
|
b317974dcc
|
made sure register values adhere to correct 32bit two's complement standard - fixes #4
|
2021-12-10 13:25:22 +01:00 |
|
Anton Lydike
|
a0259707b2
|
Released v1.0.0 to PyPi
|
2021-12-05 21:17:05 +01:00 |
|
Anton Lydike
|
e65775774a
|
extended userspace RV32I with li, la and mv instruction
|
2021-12-05 16:45:06 +01:00 |
|
Anton Lydike
|
e9c11e9a41
|
added correct instruction printing
|
2021-11-16 08:02:27 +01:00 |
|
Anton Lydike
|
0b34aea520
|
Merge pull request #1 from AntonLydike/kernel-mode
Adding limited privileged emulation using the `riscemu.priv` module
|
2021-10-10 19:58:35 +02:00 |
|
Anton Lydike
|
7ab3f8361d
|
code cleanup to increase visibility
|
2021-09-30 22:04:49 +02:00 |
|
Anton Lydike
|
d09b7a5cb1
|
overhaul of debugging info printing
|
2021-09-30 21:54:50 +02:00 |
|
Anton Lydike
|
d0c5abe845
|
added a whole lot of debugging info for privileged emulation
|
2021-09-30 20:58:44 +02:00 |
|
Anton Lydike
|
3d4d36bfe4
|
moved dependency on pyelftools into scoped function where it's used to reduce the number of dependencies required overall
|
2021-09-03 15:01:55 +02:00 |
|
Anton Lydike
|
0c96a87dcb
|
added RV32A extension, only missing LR.W and SC.W
|
2021-09-03 14:59:34 +02:00 |
|
Anton Lydike
|
3033eb9985
|
tranlsation from absolute addressed to symbol-relative names for debugging
|
2021-08-30 20:10:22 +02:00 |
|
Anton Lydike
|
ca71e196c2
|
added verbose flag and improved verbose output
|
2021-08-30 19:40:13 +02:00 |
|
Anton Lydike
|
f2d07f90b5
|
priv: added __main__ script to module which correctly configures the cpu depending on --kernel or --image options
|
2021-08-30 15:40:13 +02:00 |
|
Anton Lydike
|
0651eabe18
|
fixed how ecalls are represented and handled
|
2021-08-30 15:09:31 +02:00 |
|
Anton Lydike
|
684c858300
|
added support for IO modules
|
2021-08-26 10:48:26 +02:00 |
|
Anton Lydike
|
df9e610d14
|
forgot to commit image loader code
|
2021-08-26 10:47:47 +02:00 |
|
Anton Lydike
|
1f03449694
|
added memory image support to priv emulator
|
2021-08-26 10:46:06 +02:00 |
|
Anton Lydike
|
4c352d8567
|
[MMU] caching last used code section
|
2021-06-08 16:34:45 +02:00 |
|
Anton Lydike
|
e8685af328
|
[PrivMMU] cleaned up file formatting
|
2021-06-08 16:34:19 +02:00 |
|
Anton Lydike
|
3d07c97a52
|
[PrivCPU] improved step function performance by checking time every tenth cycle
|
2021-06-08 16:33:48 +02:00 |
|
Anton Lydike
|
60a2a8d546
|
[CSR] adding cache to mstatus register
|
2021-06-08 16:32:39 +02:00 |
|
Anton Lydike
|
6b4f38d030
|
[ElfLoader] added cache for already decoded instructions
|
2021-06-08 15:07:51 +02:00 |
|
Anton Lydike
|
05c17bc029
|
[PrivCPU] fixed debugger skipping over ebreak instructions
|
2021-06-08 14:44:13 +02:00 |
|
Anton Lydike
|
baa1f24eb7
|
[CpuTraps] fixed formatting for mcause registers
|
2021-06-08 14:42:44 +02:00 |
|
Anton Lydike
|
777717ed2e
|
[PrivRV32I] fixed csrrw instruction to correctly switch register contents
|
2021-06-08 11:36:33 +02:00 |
|
Anton Lydike
|
c7b3693740
|
[Regsietrs] ensuring register values are 32bit
|
2021-06-08 11:36:00 +02:00 |
|
Anton Lydike
|
cc598c0910
|
[PrivCPU] changed timer compare to lower equals to trigger exactly on time
|
2021-06-08 11:35:20 +02:00 |
|
Anton Lydike
|
affaa60d22
|
[PrivCPU] adding performance counter
|
2021-06-08 11:34:28 +02:00 |
|
Anton Lydike
|
48ce44993b
|
[CSR] Adding dump_mstatus method to csr
|
2021-06-08 11:32:51 +02:00 |
|
Anton Lydike
|
639f91b192
|
[decoder] removed sign extension for CSR type instructions
|
2021-06-08 11:31:58 +02:00 |
|
Anton Lydike
|
c25b9f2343
|
[PrivCPU] implemented CPU interrupt handling context switch
|
2021-06-08 00:23:09 +02:00 |
|
Anton Lydike
|
4c7f3ffe67
|
[PrivCPU] fixed perf-counter not comparing against shifted time
|
2021-06-08 00:22:30 +02:00 |
|
Anton Lydike
|
c2002cd46d
|
[PrivCPU] fixed naming for csr mtimecmp callback function
|
2021-06-08 00:21:51 +02:00 |
|
Anton Lydike
|
5b2b12507d
|
[PrivRV32I] added half od csrrs instruction (reading only)
|
2021-06-08 00:21:05 +02:00 |
|
Anton Lydike
|
052ad56310
|
[CSR] fixed call to enum value member
|
2021-06-08 00:20:25 +02:00 |
|
Anton Lydike
|
d9e5d78f87
|
[Registers] removed info when writing to zero register
|
2021-06-08 00:19:36 +02:00 |
|
Anton Lydike
|
79d913baaf
|
[decoder] fixed formatting in print_ins function
|
2021-06-08 00:19:04 +02:00 |
|
Anton Lydike
|
9278235e44
|
[decoder] fixed botched j immediate decoding
|
2021-06-08 00:18:44 +02:00 |
|
Anton Lydike
|
6351f1e84d
|
[PrivRV32I] fixed bug with blt backwards jumps missing by one
|
2021-06-06 09:55:15 +02:00 |
|
Anton Lydike
|
f14bd2b983
|
[PrivCPU, PrivRV32I] fixed bug where ebreaks where missed during debugging
|
2021-06-05 16:19:35 +02:00 |
|
Anton Lydike
|
c1110b9ce3
|
[ElfLoader] better formatting for jump and load/store instructions
|
2021-06-05 15:29:40 +02:00 |
|
Anton Lydike
|
37910018b9
|
[PrivRV32I] finally correct parsing of load/store instruction args
|
2021-06-05 15:29:06 +02:00 |
|
Anton Lydike
|
e4537f86d9
|
[PrivRV32I] implemented csrrwi instruction
|
2021-06-05 15:28:27 +02:00 |
|
Anton Lydike
|
c770cc05cf
|
[Priv Exceptions] added __str__ as __repr__ alias to CpuTrap to correctly format exceptions when printed
|
2021-06-05 15:25:39 +02:00 |
|
Anton Lydike
|
3e4920f5d9
|
[decoder] fixed bug when decoding add/sub instruction
|
2021-06-05 15:24:40 +02:00 |
|
Anton Lydike
|
849d5f4fc3
|
[decoder, ElfLoader] decoing an instruction now returns all args as int
|
2021-06-05 15:24:16 +02:00 |
|