Anton Lydike
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d0c5abe845
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added a whole lot of debugging info for privileged emulation
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2021-09-30 20:58:44 +02:00 |
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Anton Lydike
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3d4d36bfe4
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moved dependency on pyelftools into scoped function where it's used to reduce the number of dependencies required overall
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2021-09-03 15:01:55 +02:00 |
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Anton Lydike
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0c96a87dcb
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added RV32A extension, only missing LR.W and SC.W
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2021-09-03 14:59:34 +02:00 |
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Anton Lydike
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3033eb9985
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tranlsation from absolute addressed to symbol-relative names for debugging
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2021-08-30 20:10:22 +02:00 |
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Anton Lydike
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ca71e196c2
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added verbose flag and improved verbose output
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2021-08-30 19:40:13 +02:00 |
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Anton Lydike
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f2d07f90b5
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priv: added __main__ script to module which correctly configures the cpu depending on --kernel or --image options
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2021-08-30 15:40:13 +02:00 |
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Anton Lydike
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0651eabe18
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fixed how ecalls are represented and handled
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2021-08-30 15:09:31 +02:00 |
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Anton Lydike
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684c858300
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added support for IO modules
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2021-08-26 10:48:26 +02:00 |
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Anton Lydike
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df9e610d14
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forgot to commit image loader code
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2021-08-26 10:47:47 +02:00 |
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Anton Lydike
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1f03449694
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added memory image support to priv emulator
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2021-08-26 10:46:06 +02:00 |
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Anton Lydike
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4c352d8567
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[MMU] caching last used code section
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2021-06-08 16:34:45 +02:00 |
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Anton Lydike
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e8685af328
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[PrivMMU] cleaned up file formatting
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2021-06-08 16:34:19 +02:00 |
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Anton Lydike
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3d07c97a52
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[PrivCPU] improved step function performance by checking time every tenth cycle
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2021-06-08 16:33:48 +02:00 |
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Anton Lydike
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60a2a8d546
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[CSR] adding cache to mstatus register
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2021-06-08 16:32:39 +02:00 |
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Anton Lydike
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6b4f38d030
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[ElfLoader] added cache for already decoded instructions
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2021-06-08 15:07:51 +02:00 |
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Anton Lydike
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05c17bc029
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[PrivCPU] fixed debugger skipping over ebreak instructions
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2021-06-08 14:44:13 +02:00 |
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Anton Lydike
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baa1f24eb7
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[CpuTraps] fixed formatting for mcause registers
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2021-06-08 14:42:44 +02:00 |
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Anton Lydike
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777717ed2e
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[PrivRV32I] fixed csrrw instruction to correctly switch register contents
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2021-06-08 11:36:33 +02:00 |
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Anton Lydike
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c7b3693740
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[Regsietrs] ensuring register values are 32bit
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2021-06-08 11:36:00 +02:00 |
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Anton Lydike
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cc598c0910
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[PrivCPU] changed timer compare to lower equals to trigger exactly on time
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2021-06-08 11:35:20 +02:00 |
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Anton Lydike
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affaa60d22
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[PrivCPU] adding performance counter
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2021-06-08 11:34:28 +02:00 |
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Anton Lydike
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48ce44993b
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[CSR] Adding dump_mstatus method to csr
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2021-06-08 11:32:51 +02:00 |
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Anton Lydike
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639f91b192
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[decoder] removed sign extension for CSR type instructions
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2021-06-08 11:31:58 +02:00 |
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Anton Lydike
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c25b9f2343
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[PrivCPU] implemented CPU interrupt handling context switch
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2021-06-08 00:23:09 +02:00 |
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Anton Lydike
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4c7f3ffe67
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[PrivCPU] fixed perf-counter not comparing against shifted time
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2021-06-08 00:22:30 +02:00 |
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Anton Lydike
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c2002cd46d
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[PrivCPU] fixed naming for csr mtimecmp callback function
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2021-06-08 00:21:51 +02:00 |
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Anton Lydike
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5b2b12507d
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[PrivRV32I] added half od csrrs instruction (reading only)
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2021-06-08 00:21:05 +02:00 |
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Anton Lydike
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052ad56310
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[CSR] fixed call to enum value member
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2021-06-08 00:20:25 +02:00 |
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Anton Lydike
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d9e5d78f87
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[Registers] removed info when writing to zero register
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2021-06-08 00:19:36 +02:00 |
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Anton Lydike
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79d913baaf
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[decoder] fixed formatting in print_ins function
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2021-06-08 00:19:04 +02:00 |
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Anton Lydike
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9278235e44
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[decoder] fixed botched j immediate decoding
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2021-06-08 00:18:44 +02:00 |
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Anton Lydike
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6351f1e84d
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[PrivRV32I] fixed bug with blt backwards jumps missing by one
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2021-06-06 09:55:15 +02:00 |
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Anton Lydike
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f14bd2b983
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[PrivCPU, PrivRV32I] fixed bug where ebreaks where missed during debugging
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2021-06-05 16:19:35 +02:00 |
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Anton Lydike
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c1110b9ce3
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[ElfLoader] better formatting for jump and load/store instructions
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2021-06-05 15:29:40 +02:00 |
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Anton Lydike
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37910018b9
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[PrivRV32I] finally correct parsing of load/store instruction args
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2021-06-05 15:29:06 +02:00 |
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Anton Lydike
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e4537f86d9
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[PrivRV32I] implemented csrrwi instruction
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2021-06-05 15:28:27 +02:00 |
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Anton Lydike
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c770cc05cf
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[Priv Exceptions] added __str__ as __repr__ alias to CpuTrap to correctly format exceptions when printed
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2021-06-05 15:25:39 +02:00 |
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Anton Lydike
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3e4920f5d9
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[decoder] fixed bug when decoding add/sub instruction
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2021-06-05 15:24:40 +02:00 |
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Anton Lydike
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849d5f4fc3
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[decoder, ElfLoader] decoing an instruction now returns all args as int
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2021-06-05 15:24:16 +02:00 |
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Anton Lydike
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f9b0bac245
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[Priv Exceptions] fixed constructor typo in TimerInterrupt
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2021-06-05 09:56:05 +02:00 |
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Anton Lydike
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9424390b65
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[decoder] Added mret, sret, uret, wfi instruction decoding support
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2021-06-05 09:54:58 +02:00 |
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Anton Lydike
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198d14d5fb
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[Priv Exceptions] added __repr__ to CpuTrap class
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2021-06-05 09:29:20 +02:00 |
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Anton Lydike
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ca3b4099d4
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[Priv] moved CSR constants to a separate file
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2021-06-05 09:27:03 +02:00 |
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79369889f4
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[CSR] fixed method naming for _addr_to_name (now _name_to_addr)
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2021-06-04 20:37:08 +02:00 |
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de261c4c43
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[Priv] overhauled instruction architecture
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2021-06-04 20:36:33 +02:00 |
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c963fe3989
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[Priv] small fixes for overlooked things
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2021-05-26 18:40:42 +02:00 |
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85af9b992f
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[PrivCPU] overhaul of instruction cycle, adding more CSR interaction
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2021-05-25 23:50:38 +02:00 |
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7239212729
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[CSR] adding virtual csr registers
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2021-05-25 23:49:37 +02:00 |
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6653ef7e7c
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[CPU] set correct MISA
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2021-05-25 11:14:52 +02:00 |
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a1f29b9d97
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[CPU] cleaned up constructor
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2021-05-25 11:14:18 +02:00 |
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