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@ -1,5 +1,5 @@
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from abc import abstractmethod
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from abc import abstractmethod
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from .colors import *
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class RiscemuBaseException(BaseException):
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class RiscemuBaseException(BaseException):
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@abstractmethod
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@abstractmethod
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@ -16,7 +16,7 @@ class ParseException(RiscemuBaseException):
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self.data = data
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self.data = data
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def message(self):
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def message(self):
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return "{}(\"{}\", data={})".format(self.__class__.__name__, self.msg, self.data)
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return FMT_PARSE + "{}(\"{}\", data={})".format(self.__class__.__name__, self.msg, self.data) + FMT_NONE
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def ASSERT_EQ(a1, a2):
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def ASSERT_EQ(a1, a2):
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@ -55,13 +55,13 @@ class MemoryAccessException(RiscemuBaseException):
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self.op = op
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self.op = op
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def message(self):
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def message(self):
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return "{}(During {} at 0x{:08x} of size {}: {})".format(
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return FMT_MEM + "{}(During {} at 0x{:08x} of size {}: {})".format(
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self.__class__.__name__,
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self.__class__.__name__,
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self.op,
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self.op,
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self.addr,
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self.addr,
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self.size,
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self.size,
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self.msg
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self.msg
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)
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) + FMT_NONE
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class OutOfMemoryEsception(RiscemuBaseException):
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class OutOfMemoryEsception(RiscemuBaseException):
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@ -69,10 +69,10 @@ class OutOfMemoryEsception(RiscemuBaseException):
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self.action = action
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self.action = action
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def message(self):
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def message(self):
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return '{}(Ran out of memory during {})'.format(
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return + FMT_MEM + '{}(Ran out of memory during {})'.format(
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self.__class__.__name__,
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self.__class__.__name__,
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self.action
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self.action
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)
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) + FMT_NONE
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# CPU Exceptions
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# CPU Exceptions
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@ -82,10 +82,10 @@ class UnimplementedInstruction(RiscemuBaseException):
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self.ins = ins
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self.ins = ins
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def message(self):
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def message(self):
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return "{}({})".format(
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return FMT_CPU + "{}({})".format(
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self.__class__.__name__,
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self.__class__.__name__,
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repr(self.ins)
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repr(self.ins)
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)
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) + FMT_NONE
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class InvalidRegisterException(RiscemuBaseException):
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class InvalidRegisterException(RiscemuBaseException):
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@ -93,10 +93,10 @@ class InvalidRegisterException(RiscemuBaseException):
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self.reg = reg
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self.reg = reg
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def message(self):
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def message(self):
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return "{}(Invalid register {})".format(
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return FMT_CPU + "{}(Invalid register {})".format(
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self.__class__.__name__,
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self.__class__.__name__,
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self.reg
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self.reg
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)
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) + FMT_NONE
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class InvalidSyscallException(RiscemuBaseException):
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class InvalidSyscallException(RiscemuBaseException):
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@ -104,10 +104,10 @@ class InvalidSyscallException(RiscemuBaseException):
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self.scall = scall
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self.scall = scall
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def message(self):
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def message(self):
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return "{}(Invalid syscall: {})".format(
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return FMT_SYSCALL + "{}(Invalid syscall: {})".format(
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self.__class__.__name__,
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self.__class__.__name__,
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self.scall
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self.scall
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)
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) + FMT_NONE
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