diff --git a/riscemu/Exceptions.py b/riscemu/Exceptions.py
index d1f400f..22558d5 100644
--- a/riscemu/Exceptions.py
+++ b/riscemu/Exceptions.py
@@ -1,5 +1,5 @@
 from abc import abstractmethod
-
+from .colors import *
 
 class RiscemuBaseException(BaseException):
     @abstractmethod
@@ -16,7 +16,7 @@ class ParseException(RiscemuBaseException):
         self.data = data
 
     def message(self):
-        return "{}(\"{}\", data={})".format(self.__class__.__name__, self.msg, self.data)
+        return FMT_PARSE + "{}(\"{}\", data={})".format(self.__class__.__name__, self.msg, self.data) + FMT_NONE
 
 
 def ASSERT_EQ(a1, a2):
@@ -55,13 +55,13 @@ class MemoryAccessException(RiscemuBaseException):
         self.op = op
 
     def message(self):
-        return "{}(During {} at 0x{:08x} of size {}: {})".format(
+        return FMT_MEM + "{}(During {} at 0x{:08x} of size {}: {})".format(
             self.__class__.__name__,
             self.op,
             self.addr,
             self.size,
             self.msg
-        )
+        ) + FMT_NONE
 
 
 class OutOfMemoryEsception(RiscemuBaseException):
@@ -69,10 +69,10 @@ class OutOfMemoryEsception(RiscemuBaseException):
         self.action = action
 
     def message(self):
-        return '{}(Ran out of memory during {})'.format(
+        return + FMT_MEM + '{}(Ran out of memory during {})'.format(
             self.__class__.__name__,
             self.action
-        )
+        ) + FMT_NONE
 
 
 # CPU Exceptions
@@ -82,10 +82,10 @@ class UnimplementedInstruction(RiscemuBaseException):
         self.ins = ins
 
     def message(self):
-        return "{}({})".format(
+        return FMT_CPU + "{}({})".format(
             self.__class__.__name__,
             repr(self.ins)
-        )
+        ) + FMT_NONE
 
 
 class InvalidRegisterException(RiscemuBaseException):
@@ -93,10 +93,10 @@ class InvalidRegisterException(RiscemuBaseException):
         self.reg = reg
 
     def message(self):
-        return "{}(Invalid register {})".format(
+        return FMT_CPU + "{}(Invalid register {})".format(
             self.__class__.__name__,
             self.reg
-        )
+        ) + FMT_NONE
 
 
 class InvalidSyscallException(RiscemuBaseException):
@@ -104,10 +104,10 @@ class InvalidSyscallException(RiscemuBaseException):
         self.scall = scall
 
     def message(self):
-        return "{}(Invalid syscall: {})".format(
+        return FMT_SYSCALL + "{}(Invalid syscall: {})".format(
             self.__class__.__name__,
             self.scall
-        )
+        ) + FMT_NONE
 
 
 
diff --git a/riscemu/colors.py b/riscemu/colors.py
new file mode 100644
index 0000000..1ef85e8
--- /dev/null
+++ b/riscemu/colors.py
@@ -0,0 +1,21 @@
+# Colors
+
+FMT_RED = '\033[31m'
+FMT_ORANGE = '\033[33m'
+FMT_GRAY = '\033[37m'
+FMT_CYAN = '\033[36m'
+FMT_GREEN = '\033[32m'
+FMT_MAGENTA = '\033[35m'
+FMT_BLUE = '\033[34m'
+FMT_YELLOW = '\033[93m'
+
+FMT_BOLD = '\033[1m'
+FMT_NONE = '\033[0m'
+FMT_UNDERLINE = '\033[4m'
+
+FMT_ERROR = FMT_RED + FMT_BOLD
+
+FMT_MEM = FMT_CYAN + FMT_BOLD
+FMT_PARSE = FMT_CYAN + FMT_BOLD
+FMT_CPU = FMT_BLUE + FMT_BOLD
+FMT_SYSCALL = FMT_YELLOW + FMT_BOLD
diff --git a/riscemu/helpers.py b/riscemu/helpers.py
index a3e0550..f325900 100644
--- a/riscemu/helpers.py
+++ b/riscemu/helpers.py
@@ -1,5 +1,6 @@
 from math import log10, ceil, log
 from .Exceptions import NumberFormatException
+from .colors import *
 
 
 def align_addr(addr: int, to_bytes: int = 8):
@@ -56,21 +57,6 @@ def to_signed(num: int, bytes=4):
     return num
 
 
-# Colors
-
-FMT_RED = '\033[31m'
-FMT_ORANGE = '\033[33m'
-FMT_GRAY = '\033[37m'
-FMT_CYAN = '\033[36m'
-FMT_GREEN = '\033[32m'
-FMT_BOLD = '\033[1m'
-FMT_MAGENTA = '\033[35m'
-FMT_NONE = '\033[0m'
-FMT_UNDERLINE = '\033[4m'
-
-FMT_ERROR = FMT_RED + FMT_BOLD
-
-
 def create_chunks(my_list, chunk_size):
     return [my_list[i:i + chunk_size] for i in range(0, len(my_list), chunk_size)]