improved instruction parsing in RV32M

float_support
Anton Lydike 4 years ago
parent d8f46c781c
commit 7aa67cd4e1

@ -11,7 +11,11 @@ class RV32M(InstructionSet):
) )
def instruction_mulh(self, ins: 'LoadedInstruction'): def instruction_mulh(self, ins: 'LoadedInstruction'):
INS_NOT_IMPLEMENTED(ins) rd, rs1, rs2 = self.parse_rd_rs_rs(ins)
self.regs.set(
rd,
(rs1 * rs2) >> 32
)
def instruction_mulhsu(self, ins: 'LoadedInstruction'): def instruction_mulhsu(self, ins: 'LoadedInstruction'):
INS_NOT_IMPLEMENTED(ins) INS_NOT_IMPLEMENTED(ins)
@ -27,9 +31,7 @@ class RV32M(InstructionSet):
) )
def instruction_divu(self, ins: 'LoadedInstruction'): def instruction_divu(self, ins: 'LoadedInstruction'):
rd, rs1, rs2 = self.parse_rd_rs_rs(ins) rd, rs1, rs2 = self.parse_rd_rs_rs(ins, signed=False)
rs1 = to_unsigned(rs1)
rs2 = to_unsigned(rs2)
self.regs.set( self.regs.set(
rd, rd,
rs1 // rs2 rs1 // rs2
@ -43,9 +45,7 @@ class RV32M(InstructionSet):
) )
def instruction_remu(self, ins: 'LoadedInstruction'): def instruction_remu(self, ins: 'LoadedInstruction'):
rd, rs1, rs2 = self.parse_rd_rs_rs(ins) rd, rs1, rs2 = self.parse_rd_rs_rs(ins, signed=False)
rs1 = to_unsigned(rs1)
rs2 = to_unsigned(rs2)
self.regs.set( self.regs.set(
rd, rd,
rs1 % rs2 rs1 % rs2

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