From 7aa67cd4e13e3a5145fe6cbcddee9b4405737610 Mon Sep 17 00:00:00 2001 From: Anton Lydike Date: Mon, 19 Apr 2021 09:48:06 +0200 Subject: [PATCH] improved instruction parsing in RV32M --- riscemu/instructions/RV32M.py | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/riscemu/instructions/RV32M.py b/riscemu/instructions/RV32M.py index ac67d7d..15816d2 100644 --- a/riscemu/instructions/RV32M.py +++ b/riscemu/instructions/RV32M.py @@ -11,7 +11,11 @@ class RV32M(InstructionSet): ) def instruction_mulh(self, ins: 'LoadedInstruction'): - INS_NOT_IMPLEMENTED(ins) + rd, rs1, rs2 = self.parse_rd_rs_rs(ins) + self.regs.set( + rd, + (rs1 * rs2) >> 32 + ) def instruction_mulhsu(self, ins: 'LoadedInstruction'): INS_NOT_IMPLEMENTED(ins) @@ -27,9 +31,7 @@ class RV32M(InstructionSet): ) def instruction_divu(self, ins: 'LoadedInstruction'): - rd, rs1, rs2 = self.parse_rd_rs_rs(ins) - rs1 = to_unsigned(rs1) - rs2 = to_unsigned(rs2) + rd, rs1, rs2 = self.parse_rd_rs_rs(ins, signed=False) self.regs.set( rd, rs1 // rs2 @@ -43,9 +45,7 @@ class RV32M(InstructionSet): ) def instruction_remu(self, ins: 'LoadedInstruction'): - rd, rs1, rs2 = self.parse_rd_rs_rs(ins) - rs1 = to_unsigned(rs1) - rs2 = to_unsigned(rs2) + rd, rs1, rs2 = self.parse_rd_rs_rs(ins, signed=False) self.regs.set( rd, rs1 % rs2