diff --git a/riscemu/priv/PrivRV32I.py b/riscemu/priv/PrivRV32I.py
index 201807e..2be49cb 100644
--- a/riscemu/priv/PrivRV32I.py
+++ b/riscemu/priv/PrivRV32I.py
@@ -138,4 +138,6 @@ class PrivRV32I(RV32I):
 
     def parse_mem_ins(self, ins: 'LoadedInstruction') -> Tuple[str, int]:
         ASSERT_LEN(ins.args, 3)
-        return ins.get_reg(1), self.get_reg_content(ins, 0) + ins.get_imm(2)
+        addr = self.get_reg_content(ins, 1) + ins.get_imm(2)
+        reg = ins.get_reg(0)
+        return reg, addr