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implemented remu, rem, divu div and mul in RV32M

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This commit is contained in:
Anton Lydike 2021-04-19 00:05:23 +02:00
parent 157589548d
commit 2d378f2e0a
1 changed files with 29 additions and 5 deletions
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34
riscemu/instructions/RV32M.py
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@ -4,7 +4,11 @@ from ..helpers import int_from_bytes, int_to_bytes, to_unsigned, to_signed
class RV32M(InstructionSet):
def instruction_mul(self, ins: 'LoadedInstruction'):
INS_NOT_IMPLEMENTED(ins)
rd, rs1, rs2 = self.parse_rd_rs_rs(ins)
self.regs.set(
rd,
rs1 * rs2
)
def instruction_mulh(self, ins: 'LoadedInstruction'):
INS_NOT_IMPLEMENTED(ins)
@ -16,13 +20,33 @@ class RV32M(InstructionSet):
INS_NOT_IMPLEMENTED(ins)
def instruction_div(self, ins: 'LoadedInstruction'):
INS_NOT_IMPLEMENTED(ins)
rd, rs1, rs2 = self.parse_rd_rs_rs(ins)
self.regs.set(
rd,
rs1 // rs2
)
def instruction_divu(self, ins: 'LoadedInstruction'):
INS_NOT_IMPLEMENTED(ins)
rd, rs1, rs2 = self.parse_rd_rs_rs(ins)
rs1 = to_unsigned(rs1)
rs2 = to_unsigned(rs2)
self.regs.set(
rd,
rs1 // rs2
)
def instruction_rem(self, ins: 'LoadedInstruction'):
INS_NOT_IMPLEMENTED(ins)
rd, rs1, rs2 = self.parse_rd_rs_rs(ins)
self.regs.set(
rd,
rs1 % rs2
)
def instruction_remu(self, ins: 'LoadedInstruction'):
INS_NOT_IMPLEMENTED(ins)
rd, rs1, rs2 = self.parse_rd_rs_rs(ins)
rs1 = to_unsigned(rs1)
rs2 = to_unsigned(rs2)
self.regs.set(
rd,
rs1 % rs2
)