From 2d378f2e0a9baf260216fcdc71c3c0039759b57e Mon Sep 17 00:00:00 2001 From: Anton Lydike Date: Mon, 19 Apr 2021 00:05:23 +0200 Subject: [PATCH] implemented remu, rem, divu div and mul in RV32M --- riscemu/instructions/RV32M.py | 34 +++++++++++++++++++++++++++++----- 1 file changed, 29 insertions(+), 5 deletions(-) diff --git a/riscemu/instructions/RV32M.py b/riscemu/instructions/RV32M.py index 91f3495..ac67d7d 100644 --- a/riscemu/instructions/RV32M.py +++ b/riscemu/instructions/RV32M.py @@ -4,7 +4,11 @@ from ..helpers import int_from_bytes, int_to_bytes, to_unsigned, to_signed class RV32M(InstructionSet): def instruction_mul(self, ins: 'LoadedInstruction'): - INS_NOT_IMPLEMENTED(ins) + rd, rs1, rs2 = self.parse_rd_rs_rs(ins) + self.regs.set( + rd, + rs1 * rs2 + ) def instruction_mulh(self, ins: 'LoadedInstruction'): INS_NOT_IMPLEMENTED(ins) @@ -16,13 +20,33 @@ class RV32M(InstructionSet): INS_NOT_IMPLEMENTED(ins) def instruction_div(self, ins: 'LoadedInstruction'): - INS_NOT_IMPLEMENTED(ins) + rd, rs1, rs2 = self.parse_rd_rs_rs(ins) + self.regs.set( + rd, + rs1 // rs2 + ) def instruction_divu(self, ins: 'LoadedInstruction'): - INS_NOT_IMPLEMENTED(ins) + rd, rs1, rs2 = self.parse_rd_rs_rs(ins) + rs1 = to_unsigned(rs1) + rs2 = to_unsigned(rs2) + self.regs.set( + rd, + rs1 // rs2 + ) def instruction_rem(self, ins: 'LoadedInstruction'): - INS_NOT_IMPLEMENTED(ins) + rd, rs1, rs2 = self.parse_rd_rs_rs(ins) + self.regs.set( + rd, + rs1 % rs2 + ) def instruction_remu(self, ins: 'LoadedInstruction'): - INS_NOT_IMPLEMENTED(ins) + rd, rs1, rs2 = self.parse_rd_rs_rs(ins) + rs1 = to_unsigned(rs1) + rs2 = to_unsigned(rs2) + self.regs.set( + rd, + rs1 % rs2 + )