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101 lines
4.7 KiB
Markdown
101 lines
4.7 KiB
Markdown
# RiscEmu - RISC-V (userspace) emulator in python
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[](https://riscemu.readthedocs.io/en/latest/?badge=latest)
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Implementing a basic RISC-V emulator, aimed at being easily extendable. Check out the docs at [readthedocs](https://riscemu.readthedocs.io/en/latest/index.html)
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or [riscemu.datenvorr.at](https://riscemu.datenvorr.at/index.html).
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This emulator contains:
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* RISC-V Assembly parser
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* RISC-V Assembly loader
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* Emulation for parts of the basic RISC-V instruction set
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* Naive memory emulator
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* Basic implementation of some syscalls
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* A debugging environment
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## Running simple Assembly:
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A couple of basic assembly programs are provided inside `examples/`, such as [`hello-world.asm`](examples/hello-world.asm).
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You can run it by typing `python -m riscemu examples/hello-world.asm`. It will produce output similar to:
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```
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[MMU] Successfully loaded: LoadedExecutable[examples/hello-world.asm](base=0x00000100, size=24bytes, sections=data text, run_ptr=0x00000110)
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[CPU] Started running from 0x00000110 (examples/hello-world.asm)
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Hello world
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Program exited with code 0
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```
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The [`read` syscall](docs/syscalls.md) defaults to readline behaviour. Reading "true chunks" (ignoring newlines) is currently not supported.
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See the docs on [asembly](docs/assembly.md) for more detail on how to write assembly code for this emulator.
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See the [list of implemented syscalls](docs/syscalls.md) for more details on how to syscall.
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Currently, symbols (such as `main` or `loop`) are looked-up at runtime. This allows for better debugging, I believe.
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Basic IO should work, as open, read, write and close are supported for stdin/stdout/stderr and even aribtrary file paths (if enabled)
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When trying to run an assembly program, the emulator first tries to find a symbol named `_start`, then a symbol named `main`. if both
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symbols were not found in the file, it simply starts at the beginning of the `.text` segment.
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## Using the CLI:
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*Current CLI is not final, options may change frequently until a stable version is reached*
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This is how the interface is used:
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```
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usage: riscemu [-h] [--options OPTIONS] [--syscall-opts SYSCALL_OPTS] [--instruction-sets INSTRUCTION_SETS] [--stack_size stack-size] file.asm [file.asm ...]
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OPTIONS and SYSCALL_OPTIONS is a list of comma-separated flags that will be enabled
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--options OPTIONS: (-o)
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disable_debug Disable the ebreak and sbreak instructions
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no_syscall_symbols Don't make syscall symbols globally available
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fail_on_ex Do not launch an interactive debugger when the CPU loop catches an exception
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add_accept_imm accept "add rd, rs, imm" instructions, even though they are not standard
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--syscall-opts SYSCALL_OPTS: (-so)
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Options to control syscall behaviour
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fs_access Allow access to the filesystem
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disable_io Disallow reading/writing from stdin/stdout/stderr
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--instruction-sets INSTRUCTION_SETS: (-is)
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A list of comma separated instruction sets you want to load:
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Currently implemented: RV32I, RV32M
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```
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If multiple files are specified, all are loaded into memeory, but only the last one is executed. This might be improved
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later, maybe the `_init` section of each binary is executed before the main loop starts?
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If `stack_size` is greater than zero, a stack is allocated and initialized, with the `sp` register pointing to the end of the stack.
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## Debugging
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Debugging is done using the `ebreak` (formerly `sbreak`) instruction, which will launch a debugging session if encountered.
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See [docs/debugging.md](docs/debugging.md) for more info.
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## The source code:
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Check out the [documentation](https://riscemu.readthedocs.io/en/latest/riscemu.html).
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## Accessing local documentation:
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To generate your local documentation, first install everything in `sphinx-docs/requirements.txt`. Then run `./generate-docs.sh`, which will
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generate and make all doc files for you. Finally, you can open the docs locall by runnint `open sphinx-docs/build/html/index.html`.
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## Resources:
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* Pseudo ops: https://www.codetd.com/article/8981522
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* detailed instruction definition: https://msyksphinz-self.github.io/riscv-isadoc/html/rvi.html#add
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* RISC-V reference card: https://www.cl.cam.ac.uk/teaching/1617/ECAD+Arch/files/docs/RISCVGreenCardv8-20151013.pdf
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## TODO:
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* Currently registers don't enforce 32 bit (no overflows etc)
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* Correctly handle 12 and 20 bit immediate (currently not limited to bits at all)
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* Add a cycle limit to the options and CPU to catch infinite loops
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* Move away from `print` and use `logging.logger` instead
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* Writer proper tests
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