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71 lines
2.7 KiB
Markdown
71 lines
2.7 KiB
Markdown
# RISC-V (userspace) emulator in python
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Implementing a basic RISC-V emulator, aimed at being easily extendable.
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This emulator contains:
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* RISC-V Assembly parser
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* RISC-V Assembly loader
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* Emulation for parts of the basic RISC-V instruction set
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* Naive memory emulator
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* Basic implementation of some syscalls
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* A debugging environment
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## Running simple Assembly:
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A couple of basic assembly programs are provided inside `examples/`, such as [`hello-world.asm`](examples/hello-world.asm).
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You can run it by typing `python -m riscemu examples/hello-world.asm`. It will produce output similar to:
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```
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Successfully loaded: LoadedExecutable[examples/hello-world.asm](base=0x00000100, size=24bytes, sections=data text, run_ptr=0x00000110)
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Hello world
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Program exited with code 0
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```
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See the docs on [asembly](docs/assembly.md) and [the cpu](docs/CPU.md) for more detail on how to write assembly code for this emulator.
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See the [list of implemented syscalls](docs/syscalls.md) for more details on how to syscall.
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Currently, symbols (such as `main:`) are looked-up at runtime. This allows for better debugging, I believe.
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Basic IO should work, as open, read, write and close are supported for stdin/stdout/stderr and even aribtrary file paths (if enabled)
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## Using the CLI:
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*Current CLI is not final, options may change frequently until a stable version is reached*
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This is how the interface is used:
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```
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riscemu [--options OPTIONS] [--syscall-option SYSCALL_OPTIONS] [--default_stack_size] file.asm [file.asm ...]
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OPTIONS and SYSCALL_OPTIONS is a list of comma-separated flags that will be enabled
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OPTIONS:
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disable_debug Disable the ebreak and sbreak instructions
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no_syscall_symbols Don't make syscall symbols globally available
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fail_on_ex Do not launch an interactive debugger when the CPU loop catches an exception
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SYSCALL_OPTIONS:
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fs_access Allow access to the filesystem
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disable_io Disallow reading/writing from stdin/stdout/stderr
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```
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If multiple files are specified, all are loaded into memeory, but only the last one is executed. This might be improved
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later, maybe the `_init` section of each binary is executed before the main loop starts?
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## Debugging
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See [docs/debugging.md](docs/debugging.md) for more info.
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![debuggin the fibs program](docs/debug-session.png)
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## Resources:
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* Pseudo ops: https://www.codetd.com/article/8981522
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* RISC-V reference card: https://www.cl.cam.ac.uk/teaching/1617/ECAD+Arch/files/docs/RISCVGreenCardv8-20151013.pdf
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## TODO:
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* Move cpu instructions to different file, allow for instruction set selection and composition
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* Add a cycle limit to the options and CPU to catch infinite loops
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* Move away from `print` and use `logging.logger` instead
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