runtime: add a basic stdlib and crt0 file

.idea/misc.xml

@@ -1,4 +1,4 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <project version="4">
-  <component name="ProjectRootManager" version="2" project-jdk-name="Python 3.10 (riscemu)" project-jdk-type="Python SDK" />
+  <component name="ProjectRootManager" version="2" project-jdk-name="Python 3.8 (riscemu)" project-jdk-type="Python SDK" />
 </project>

.idea/riscemu.iml

@@ -10,7 +10,7 @@
       <excludeFolder url="file://$MODULE_DIR$/riscemu.egg-info" />
       <excludeFolder url="file://$MODULE_DIR$/build" />
     </content>
-    <orderEntry type="jdk" jdkName="Python 3.10 (riscemu)" jdkType="Python SDK" />
+    <orderEntry type="inheritedJdk" />
     <orderEntry type="sourceFolder" forTests="false" />
   </component>
 </module>

CHANGELOG.md

@@ -1,5 +1,21 @@
 # Changelog
 
+## Upcoming 2.0.6
+
+**Planned:**
+ - Add a floating point unit
+ - Add a crt0.s
+ - Add `mmap2` syscall with code 192
+
+## 2.0.5
+
+ - Added unlimited register mode with `-o unlimited_regs`
+
+## 2.0.4
+
+ - Bugfix: fix a sign issue in instruction parsing for `rd, rs, rs` format
+ - Bugfix: respect `conf.debug_instruction` setting
+
 ## 2.0.3 - 2022-04-18
 
  - Syscalls: cleaned up formatting and added instructions for extensions

examples/lib/crt0.s

@@ -0,0 +1,14 @@
+// A minimal crt0.s that works along the stdlib.s file provided to give
+// some resemblance of a functioning compilation target :)
+//
+// Copyright (c) 2023 Anton Lydike
+// SPDX-License-Identifier: MIT
+
+.text
+
+.globl _start
+_start:
+        // TODO: read argc, argv from a0, a1
+        // maybe even find envptr?
+        jal main
+        jal exit

examples/lib/stdlib.s

@@ -0,0 +1,176 @@
+// A very basic implementation of a stdlib.h but in assembly.
+// should(tm) work with riscemu.
+//
+// Copyright (c) 2023 Anton Lydike
+// SPDX-License-Identifier: MIT
+
+.data
+
+_rand_seed: 
+.word   0x76767676
+_atexit_calls:
+// leave room for 8 atexit handlers here for now
+.word   0x00, 0x00, 0x00, 0x00
+.word   0x00, 0x00, 0x00, 0x00
+_atexit_count:
+.word   0x00
+
+_malloc_base_ptr:
+// first word is a pointer to some space
+// second word is the offset inside that space
+// space is always MALLOC_PAGE_SIZE bytes
+.word   0x00, 0x00
+.equ    MALLOC_PAGE_SIZE 4069
+
+.text
+
+// malloc/free
+
+.globl malloc
+.globl free
+
+// malloc(size_t size)
+malloc:
+        // set aside size in s0
+        sw  s0, -4(sp)
+        mv  a0, s0
+        la  t0, _malloc_base_ptr
+        lw  t1, 0(t0)
+        beq t1, zero, _malloc_init
+_malloc_post_init:
+        // if we are here, we always have
+        // t0 = (&_malloc_base_ptr)
+        // t1 = *(&_malloc_base_ptr)
+        // new we load
+        // t2 = base_ptr_offset
+        lw  t2, 4(t0)
+        // add allocated size to offset
+        add t2, t2, s0
+        // check for overflow
+        li  t4, MALLOC_PAGE_SIZE
+        bge t2, t4, _malloc_fail
+        // save the new offset
+        sw  t2, 4(t0)
+        // calculate base_ptr + offset
+        add a0, t2, t1
+        // return that
+        lw  s0, -4(sp)
+        ret
+
+_malloc_init:
+        // call mmap2()
+        li  a0, 0       // addr = 0, let OS choose address
+        li  a1, 4096    // size
+        li  a2, 3       // PROT_READ   | PROT_WRITE
+        li  a3, 5       // MAP_PRIVATE | MAP_ANONYMOUS
+        li  a7, SCALL_MMAP2
+        ecall           // invoke syscall
+        // check for error code
+        li  t0, -1
+        beq a0, t0, _malloc_fail
+        // if succeeded, load &_malloc_base_ptr
+        la  t0, _malloc_base_ptr
+        // put value of _malloc_base_ptr into t1
+        mv  a0, t1
+        // save base ptr to _malloc_base_ptr
+        sw  t1, 0(t0)
+        // jump to post_init
+        j   _malloc_post_init
+_malloc_fail:
+        li a0, 0
+        ret
+
+// free is a nop, that's valid, but not very good^^
+free:
+        ret
+
+
+
+// exit, atexit
+.globl exit
+.globl atexit
+
+// we can happily use saved registers here because we don't care at all if we
+// destroy the calling registers. This is __noreturn__ anyways!
+// register layout:
+// s0 = &_atexit_count
+// s2 = &_atexit_calls
+// s1 = updated value of atexit
+exit:
+        la      s0, _atexit_count       // s0 = &_atexit_count
+        lw      s1, 0(s0)               // s1 = *(&_atexit_count)
+        // exit if no atexit() calls remain
+        beq     s1, zero, _exit
+        // decrement
+        addi    s1, s1, -4              // s1--
+        // save decremented value
+        sw      s1, 0(s0)               // _atexit_count = s1
+        li      s2, _atexit_calls
+        add     s1, s1, s2              // s1 = &_atexit_calls + (s1)
+        lw      s1, 0(s1)               // s1 = *s1
+        la      ra, exit                // set ra up to point to exit
+        jalr    zero, s1, 0             // jump to address in s1
+        // jalr will call the other function, which will then return back
+        // to the beginning of exit.
+_exit:
+        li      a0, 0
+        li      a7, 93
+        ecall
+
+// atexit a0 = funcptr
+atexit:
+        sw      t0, -4(sp)
+        sw      t2, -8(sp)
+        // load _atexit_count
+        la      t0, _atexit_count
+        lw      t2, 0(t0)
+        // if >= 8, fail
+        li      t1, 8
+        bge     t2, t1, _atexit_fail
+        // increment atexit_count by 4 (one word)
+        addi    t2, t2, 4
+        sw      t2, 0(t0)
+        // load address of _atexit_calls
+        la      t0, _atexit_calls
+        // add new _atexit_count to _atexit_calls
+        add     t0, t0, t2
+        sw      a0, -4(t0)
+        li      a0, 0
+        lw      t0, -4(sp)
+        lw      t2, -8(sp)
+        ret
+
+_atexit_fail:
+        li      a0, -1
+        lw      s0, -4(sp)
+        lw      s1, -8(sp)
+        ret
+
+
+
+        
+
+
+// rand, srand
+
+.globl  rand
+.globl  srand
+
+// simple xorshift rand implementation
+rand:
+        // load seed
+        la  t1, _rand_seed
+        lw  a0, 0(t1)
+        // three rounds of shifts:
+        sll a0, t0, 13          // x ^= x << 13;
+        srl a0, t0, 17          // x ^= x >> 17;
+        sll a0, t0, 5           // x ^= x << 5;
+	    sw  a0, 0(t1)
+	    ret
+
+srand:
+        la  t1, _rand_seed
+        sw  a0, 0(t1)
+        ret
+
+

riscemu/MMU.py

@@ -252,7 +252,7 @@ class MMU:
             sec.base = at_addr
             self.sections.append(sec)
             self._update_state()
-            return True
+        return True
 
     def _update_state(self):
         """
@@ -281,14 +281,3 @@ class MMU:
             return sec.context
 
         return InstructionContext()
-
-    def report_addr(self, addr: T_AbsoluteAddress):
-        sec = self.get_sec_containing(addr)
-        if not sec:
-            print("addr is in no section!")
-            return
-        owner = [b for b in self.programs if b.name == sec.owner]
-        if owner:
-            print("owned by: {}".format(owner[0]))
-
-        print("{}: 0x{:0x} + 0x{:0x}".format(name, val, addr - val))

riscemu/instructions/RV32I.py

@@ -269,9 +269,10 @@ class RV32I(InstructionSet):
     def instruction_jalr(self, ins: 'Instruction'):
         ASSERT_LEN(ins.args, 2)
         reg = ins.get_reg(0)
-        addr = ins.get_imm(1)
+        base = ins.get_reg(1)
+        addr = ins.get_imm(2)
         self.regs.set(reg, Int32(self.pc))
-        self.pc = addr
+        self.pc = self.regs.get(base).unsigned_value + addr
 
     def instruction_ret(self, ins: 'Instruction'):
         ASSERT_LEN(ins.args, 0)

riscemu/syscall.py

@@ -6,8 +6,10 @@ SPDX-License-Identifier: MIT
 
 import sys
 from dataclasses import dataclass
+from math import log2, ceil
 from typing import Dict, IO
 
+from .types import BinaryDataMemorySection, MemoryFlags
 from .colors import FMT_SYSCALL, FMT_NONE
 from .types import Int32, CPU
 from .types.exceptions import InvalidSyscallException
@@ -16,6 +18,7 @@ SYSCALLS = {
     63: 'read',
     64: 'write',
     93: 'exit',
+    192: 'mmap2',
     1024: 'open',
     1025: 'close',
 }
@@ -27,6 +30,18 @@ dictionary and implement a method with the same name on the SyscallInterface
 class.
 """
 
+ADDITIONAL_SYMBOLS = {
+    'MAP_PRIVATE': 1<<0,
+    'MAP_SHARED': 1<<1,
+    'MAP_ANON': 1<<2,
+    'MAP_ANONYMOUS': 1<<2,
+    'PROT_READ': 1<<0,
+    'PROT_WRITE': 1<<1,
+}
+"""
+A set of additional symbols that are used by various syscalls.
+"""
+
 OPEN_MODES = {
     0: 'rb',
     1: 'wb',
@@ -56,7 +71,7 @@ class Syscall:
             self.id, self.name
         )
 
-    def ret(self, code):
+    def ret(self, code: int | Int32):
         self.cpu.regs.set('a0', Int32(code))
 
 
@@ -66,10 +81,14 @@ def get_syscall_symbols():
 
     :return: dictionary of all syscall symbols (SCALL_<name> -> id)
     """
-    return {
+    items: Dict[str, int] = {
         ('SCALL_' + name.upper()): num for num, name in SYSCALLS.items()
     }
 
+    items.update(ADDITIONAL_SYMBOLS)
+
+    return items
+
 
 class SyscallInterface:
     """
@@ -198,6 +217,57 @@ class SyscallInterface:
         scall.cpu.halted = True
         scall.cpu.exit_code = scall.cpu.regs.get('a0').value
 
+    def mmap2(self, scall: Syscall):
+        """
+        mmap2 syscall:
+
+        void *mmap(void *addr, size_t length, int prot, int flags,
+                  int fd, off_t offset);
+
+        Only supported modes:
+        addr  = <any>
+        prot  = either PROT_READ or PROT_READ | PROT_WRITE
+        flags = MAP_PRIVATE | MAP_ANONYMOUS
+        fd    = <ignored>
+        off_t = <ignored>
+        """
+        addr = scall.cpu.regs.get('a0').unsigned_value
+        size = scall.cpu.regs.get('a1').unsigned_value
+        prot = scall.cpu.regs.get('a2').unsigned_value
+        flags = scall.cpu.regs.get('a3').unsigned_value
+
+        # error out if prot is not 1 or 3:
+        # 1 = PROT_READ
+        # 3 = PROT_READ | PROT_WRITE
+        if prot != 1 and prot != 3:
+            return scall.ret(-1)
+
+        # round size up to multiple of 4096
+        size = 4096 * ceil(size / 4096)
+        section = BinaryDataMemorySection(
+            bytearray(size),
+            '.data.runtime-allocated',
+            None,
+            'system',
+            base=addr,
+            flags=MemoryFlags(read_only=prot != 3, executable=False)
+        )
+
+        # try to insert section
+        if scall.cpu.mmu.load_section(section, addr != 0):
+            return scall.ret(section.base)
+        # if that failed, and we tried to force an address,
+        # try again at any address
+        elif addr != 0:
+            section.base = 0
+            if scall.cpu.mmu.load_section(section):
+                return scall.ret(section.base)
+        # if that didn't work, return error
+        return scall.ret(-1)
+
+
+
+
     def __repr__(self):
         return "{}(\n\tfiles={}\n)".format(
             self.__class__.__name__,

riscemu/types/cpu.py

@@ -1,12 +1,16 @@
 import typing
 from abc import ABC, abstractmethod
-from typing import List, Type, Callable, Set, Dict
+from typing import List, Type, Callable, Set, Dict, TYPE_CHECKING
 
 from ..registers import Registers
 from ..config import RunConfig
 from ..colors import FMT_RED, FMT_NONE, FMT_ERROR, FMT_CPU
 from . import T_AbsoluteAddress, Instruction, Program, ProgramLoader
 
+if TYPE_CHECKING:
+    from .. import MMU
+    from ..instructions import InstructionSet
+
 
 class CPU(ABC):
     # static cpu configuration