base: add debug instructions

examples/static-data.asm

@@ -0,0 +1,20 @@
+.data
+my_data:
+.word   0x11223344, 0x55667788, 0x9900aabb, 0xccddeeff
+
+.text
+main:
+        // load base address into t0
+        la  t0, my_data
+        // begin loading words and printing them
+        lw  a0, 0(t0)
+        print.uhex a0
+        lw  a0, 4(t0)
+        print.uhex a0
+        lw  a0, 8(t0)
+        print.uhex a0
+        lw  a0, 12(t0)
+        print.uhex a0
+        // exit
+        li  a7, 93
+        ecall

riscemu/IO/IOModule.py

@@ -1,4 +1,4 @@
-from abc import ABC, abstractmethod
+from abc import ABC
 from typing import Optional
 
 from riscemu.types import MemorySection, MemoryFlags, T_RelativeAddress

riscemu/__init__.py

@@ -25,4 +25,4 @@ from .parser import tokenize, parse_tokens, AssemblyFileLoader
 
 __author__ = "Anton Lydike <Anton@Lydike.com>"
 __copyright__ = "Copyright 2022 Anton Lydike"
-__version__ = '2.0.4'
+__version__ = '2.0.5'

riscemu/instructions/RV_Debug.py

@@ -0,0 +1,19 @@
+from .instruction_set import InstructionSet, Instruction
+
+
+class RV_Debug(InstructionSet):
+    def instruction_print(self, ins: Instruction):
+        reg = ins.get_reg(0)
+        print("register {} contains value {}".format(reg, self.regs.get(reg)))
+
+    def instruction_print_uint(self, ins: Instruction):
+        reg = ins.get_reg(0)
+        print("register {} contains value {}".format(reg, self.regs.get(reg).unsigned_value))
+
+    def instruction_print_hex(self, ins: Instruction):
+        reg = ins.get_reg(0)
+        print("register {} contains value {}".format(reg, hex(self.regs.get(reg))))
+
+    def instruction_print_uhex(self, ins: Instruction):
+        reg = ins.get_reg(0)
+        print("register {} contains value {}".format(reg, hex(self.regs.get(reg).unsigned_value)))

riscemu/instructions/__init__.py

@@ -10,7 +10,8 @@ from .instruction_set import InstructionSet, Instruction
 from .RV32M import RV32M
 from .RV32I import RV32I
 from .RV32A import RV32A
+from .RV_Debug import RV_Debug
 
 InstructionSetDict = {
-    v.__name__: v for v in [RV32I, RV32M, RV32A]
+    v.__name__: v for v in [RV32I, RV32M, RV32A, RV_Debug]
 }