From c7b36937402545d95e1f42aab450773240d04651 Mon Sep 17 00:00:00 2001 From: Anton Lydike Date: Tue, 8 Jun 2021 11:36:00 +0200 Subject: [PATCH] [Regsietrs] ensuring register values are 32bit --- riscemu/Registers.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/riscemu/Registers.py b/riscemu/Registers.py index d3dfe47..ab74821 100644 --- a/riscemu/Registers.py +++ b/riscemu/Registers.py @@ -103,7 +103,7 @@ class Registers: reg = 's1' if mark_set: self.last_set = reg - self.vals[reg] = val + self.vals[reg] = val & (2**32 - 1) return True def get(self, reg, mark_read=True):