From b317974dccfcc8cb538a91a2ed04ca2482b832ab Mon Sep 17 00:00:00 2001 From: Anton Lydike Date: Fri, 10 Dec 2021 13:25:22 +0100 Subject: [PATCH] made sure register values adhere to correct 32bit two's complement standard - fixes #4 --- riscemu/Registers.py | 6 +----- riscemu/helpers.py | 13 +++++++++++++ 2 files changed, 14 insertions(+), 5 deletions(-) diff --git a/riscemu/Registers.py b/riscemu/Registers.py index 3cc10db..df282c1 100644 --- a/riscemu/Registers.py +++ b/riscemu/Registers.py @@ -104,11 +104,7 @@ class Registers: if mark_set: self.last_set = reg # check 32 bit signed bounds - if val < -2147483648: - val = -2147483648 - elif val > 2147483647: - val = 2147483647 - self.vals[reg] = val + self.vals[reg] = bind_twos_complement(val) return True def get(self, reg, mark_read=True): diff --git a/riscemu/helpers.py b/riscemu/helpers.py index 85b64af..7722d9f 100644 --- a/riscemu/helpers.py +++ b/riscemu/helpers.py @@ -92,3 +92,16 @@ def format_bytes(byte_arr: bytearray, fmt: str, group: int = 1, highlight: int = highlight) if fmt == 'ascii': return "".join(repr(chr(b))[1:-1] for b in byte_arr) + + +def bind_twos_complement(val): + """ + does over/underflows for 32 bit two's complement numbers + :param val: + :return: + """ + if val < -2147483648: + return val + 4294967296 + elif val > 2147483647: + return val - 4294967296 + return val \ No newline at end of file