preparations for sphinx documentation generation
This commit is contained in:
parent
6e6ce90e9a
commit
819d57e3c8
0
.readthedocs.yaml
Normal file
0
.readthedocs.yaml
Normal file
@ -11,7 +11,7 @@ from typing import Tuple, List, Dict, Callable, Type
|
||||
|
||||
from .Tokenizer import RiscVTokenizer
|
||||
|
||||
from .Syscall import SyscallInterface
|
||||
from .Syscall import SyscallInterface, get_syscall_symbols
|
||||
from .Exceptions import RiscemuBaseException, LaunchDebuggerException
|
||||
from .MMU import MMU
|
||||
from .Config import RunConfig
|
||||
@ -19,6 +19,8 @@ from .Registers import Registers
|
||||
from .debug import launch_debug_session
|
||||
from .colors import FMT_CPU, FMT_NONE, FMT_ERROR
|
||||
|
||||
import riscemu
|
||||
|
||||
import typing
|
||||
|
||||
if typing.TYPE_CHECKING:
|
||||
@ -32,7 +34,7 @@ class CPU:
|
||||
|
||||
It is initialized with a configuration and a list of instruction sets.
|
||||
"""
|
||||
def __init__(self, conf: RunConfig, instruction_sets: List[Type['InstructionSet']]):
|
||||
def __init__(self, conf: RunConfig, instruction_sets: List[Type['riscemu.InstructionSet']]):
|
||||
"""
|
||||
Creates a CPU instance.
|
||||
|
||||
@ -53,7 +55,7 @@ class CPU:
|
||||
self.syscall_int = SyscallInterface()
|
||||
|
||||
# load all instruction sets
|
||||
self.instruction_sets: List['InstructionSet'] = list()
|
||||
self.instruction_sets: List[riscemu.InstructionSet] = list()
|
||||
self.instructions: Dict[str, Callable[[LoadedInstruction], None]] = dict()
|
||||
for set_class in instruction_sets:
|
||||
ins_set = set_class(self)
|
||||
@ -72,13 +74,13 @@ class CPU:
|
||||
"""
|
||||
return RiscVTokenizer(tokenizer_input, self.all_instructions())
|
||||
|
||||
def load(self, e: 'Executable'):
|
||||
def load(self, e: riscemu.Executable):
|
||||
"""
|
||||
Load an executable into Memory
|
||||
"""
|
||||
return self.mmu.load_bin(e)
|
||||
|
||||
def run_loaded(self, le: 'LoadedExecutable'):
|
||||
def run_loaded(self, le: 'riscemu.LoadedExecutable'):
|
||||
"""
|
||||
Run a loaded executable
|
||||
"""
|
||||
|
@ -4,9 +4,14 @@ RiscEmu (c) 2021 Anton Lydike
|
||||
SPDX-License-Identifier: BSD-2-Clause
|
||||
"""
|
||||
|
||||
import typing
|
||||
|
||||
from abc import abstractmethod
|
||||
from .colors import *
|
||||
|
||||
if typing.TYPE_CHECKING:
|
||||
from .Executable import LoadedInstruction
|
||||
|
||||
|
||||
class RiscemuBaseException(BaseException):
|
||||
@abstractmethod
|
||||
@ -93,6 +98,7 @@ class OutOfMemoryException(RiscemuBaseException):
|
||||
|
||||
# CPU Exceptions
|
||||
|
||||
|
||||
class UnimplementedInstruction(RiscemuBaseException):
|
||||
def __init__(self, ins: 'LoadedInstruction'):
|
||||
self.ins = ins
|
||||
|
@ -17,6 +17,8 @@ from .Executable import Executable, LoadedExecutable
|
||||
|
||||
from .ExecutableParser import ExecutableParser
|
||||
|
||||
from .instructions import *
|
||||
|
||||
from .MMU import MMU
|
||||
from .Registers import Registers
|
||||
from .Syscall import SyscallInterface, Syscall
|
||||
|
@ -9,6 +9,7 @@ from typing import Tuple, Callable, Dict
|
||||
from abc import ABC
|
||||
from ..CPU import CPU
|
||||
from ..helpers import ASSERT_LEN, ASSERT_IN, to_unsigned
|
||||
from ..Executable import LoadedInstruction
|
||||
|
||||
|
||||
class InstructionSet(ABC):
|
||||
|
@ -11,6 +11,7 @@ from ..colors import FMT_DEBUG, FMT_NONE
|
||||
from ..debug import launch_debug_session
|
||||
from ..Exceptions import LaunchDebuggerException
|
||||
from ..Syscall import Syscall
|
||||
from ..Executable import LoadedInstruction
|
||||
|
||||
|
||||
class RV32I(InstructionSet):
|
||||
|
0
sphinx-docs/.gitignore
vendored
Normal file
0
sphinx-docs/.gitignore
vendored
Normal file
Loading…
Reference in New Issue
Block a user