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@ -3,19 +3,20 @@ RiscEmu (c) 2021 Anton Lydike
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SPDX-License-Identifier: MIT
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SPDX-License-Identifier: MIT
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"""
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"""
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import sys
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import time
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import time
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from riscemu.CPU import *
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from riscemu.CPU import *
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from .CSR import CSR
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from .CSR import CSR
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from .ElfLoader import ElfBinaryFileLoader
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from .Exceptions import *
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from .Exceptions import *
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from .PrivMMU import PrivMMU
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from .ImageLoader import MemoryImageLoader
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from .PrivRV32I import PrivRV32I
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from .PrivRV32I import PrivRV32I
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from .privmodes import PrivModes
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from .privmodes import PrivModes
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from ..IO import TextIO
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from ..instructions import RV32A, RV32M
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from ..instructions import RV32A, RV32M
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from ..types import Program
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if typing.TYPE_CHECKING:
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if typing.TYPE_CHECKING:
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from riscemu import types, LoadedExecutable, LoadedInstruction
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from riscemu.instructions.instruction_set import InstructionSet
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from riscemu.instructions.instruction_set import InstructionSet
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@ -38,21 +39,20 @@ class PrivCPU(CPU):
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controls the resolution of the time csr register (in nanoseconds)
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controls the resolution of the time csr register (in nanoseconds)
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"""
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"""
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INS_XLEN = 4
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pending_traps: List[CpuTrap]
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"""
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"""
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Size of an instruction in memory. Should be 4, but since our loading code is shit, instruction take up
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A list of traps which are pending to be handled
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the equivalent of "1 byte" (this is actually impossible)
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"""
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"""
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def __init__(self, conf):
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def __init__(self, conf):
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super().__init__(conf, [PrivRV32I, RV32M, RV32A])
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super().__init__(MMU(), [PrivRV32I, RV32M, RV32A], conf)
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# start in machine mode
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# start in machine mode
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self.mode: PrivModes = PrivModes.MACHINE
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self.mode: PrivModes = PrivModes.MACHINE
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self.syscall_int = None
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self.launch_debug = False
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self.pending_traps: List[CpuTrap] = list()
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self.pending_traps: List[CpuTrap] = list()
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self.exit_code = 0
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self._time_start = 0
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self._time_start = 0
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self._time_timecmp = 0
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self._time_timecmp = 0
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self._time_interrupt_enabled = False
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self._time_interrupt_enabled = False
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@ -63,45 +63,37 @@ class PrivCPU(CPU):
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# init csr
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# init csr
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self._init_csr()
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self._init_csr()
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def _run(self, verbose=False):
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def run(self, verbose=False):
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if self.pc <= 0:
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if self.pc <= 0:
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return False
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return False
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ins = None
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launch_debug = False
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try:
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try:
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while not self.exit:
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while not self.halted:
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self.step(verbose)
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self.step(verbose)
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except RiscemuBaseException as ex:
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except RiscemuBaseException as ex:
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if isinstance(ex, LaunchDebuggerException):
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if isinstance(ex, LaunchDebuggerException):
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self.launch_debug = True
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launch_debug = True
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self.pc += self.INS_XLEN
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self.pc += self.INS_XLEN
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if self.exit:
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if self.halted:
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print()
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print()
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print(FMT_CPU + "Program exited with code {}".format(self.exit_code) + FMT_NONE)
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print(FMT_CPU + "[CPU] System halted with code {}".format(self.exit_code) + FMT_NONE)
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sys.exit(self.exit_code)
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sys.exit(self.exit_code)
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elif self.launch_debug:
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self.launch_debug = False
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elif launch_debug:
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launch_debug_session(self, self.mmu, self.regs,
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launch_debug_session(self)
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"Launching debugger:")
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if not self.debugger_active:
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if not self.debugger_active:
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self._run(verbose)
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self.run(verbose)
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else:
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else:
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print()
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print()
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print(FMT_CPU + "Program stopped without exiting - perhaps you stopped the debugger?" + FMT_NONE)
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print(FMT_CPU + "[CPU] System stopped without halting - perhaps you stopped the debugger?" + FMT_NONE)
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def load(self, e: riscemu.base_types):
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def launch(self, program: Program, verbose: bool = False):
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raise NotImplementedError("Not supported!")
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def run_loaded(self, le: 'riscemu.LoadedExecutable'):
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raise NotImplementedError("Not supported!")
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def get_tokenizer(self, tokenizer_input):
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raise NotImplementedError("Not supported!")
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def run(self, verbose: bool = False):
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print(FMT_CPU + '[CPU] Started running from 0x{:08X} ({})'.format(self.pc, "kernel") + FMT_NONE)
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print(FMT_CPU + '[CPU] Started running from 0x{:08X} ({})'.format(self.pc, "kernel") + FMT_NONE)
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self._time_start = time.perf_counter_ns() // self.TIME_RESOLUTION_NS
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self._time_start = time.perf_counter_ns() // self.TIME_RESOLUTION_NS
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self._run(self.conf.verbosity > 1)
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self.run(self.conf.verbosity > 1 or verbose)
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def _init_csr(self):
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def _init_csr(self):
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# set up CSR
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# set up CSR
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@ -184,7 +176,7 @@ class PrivCPU(CPU):
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if not (len(self.pending_traps) > 0 and self.csr.get_mstatus('mie')):
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if not (len(self.pending_traps) > 0 and self.csr.get_mstatus('mie')):
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return
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return
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# select best interrupt
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# select best interrupt
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# TODO: actually select based on the official ranking
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# FIXME: actually select based on the official ranking
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trap = self.pending_traps.pop() # use the most recent trap
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trap = self.pending_traps.pop() # use the most recent trap
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if self.conf.verbosity > 0:
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if self.conf.verbosity > 0:
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print(FMT_CPU + "[CPU] taking trap {}!".format(trap) + FMT_NONE)
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print(FMT_CPU + "[CPU] taking trap {}!".format(trap) + FMT_NONE)
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@ -209,7 +201,7 @@ class PrivCPU(CPU):
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if mtvec & 0b11 == 1:
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if mtvec & 0b11 == 1:
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self.pc = (mtvec & 0b11111111111111111111111111111100) + (trap.code * 4)
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self.pc = (mtvec & 0b11111111111111111111111111111100) + (trap.code * 4)
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self.record_perf_profile()
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self.record_perf_profile()
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if len(self._perf_counters) % 100 == 0:
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if len(self._perf_counters) > 100:
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self.show_perf()
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self.show_perf()
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def show_perf(self):
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def show_perf(self):
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@ -225,11 +217,6 @@ class PrivCPU(CPU):
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continue
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continue
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cps = (cycle - cycled) / (time_ns - timed) * 1000000000
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cps = (cycle - cycled) / (time_ns - timed) * 1000000000
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# print(" {:03d} cycles in {:08d}ns ({:.2f} cycles/s)".format(
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# cycle - cycled,
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# time_ns - timed,
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# cps
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# ))
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cycled = cycle
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cycled = cycle
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timed = time_ns
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timed = time_ns
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cps_list.append(cps)
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cps_list.append(cps)
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@ -238,3 +225,9 @@ class PrivCPU(CPU):
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def record_perf_profile(self):
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def record_perf_profile(self):
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self._perf_counters.append((time.perf_counter_ns(), self.cycle))
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self._perf_counters.append((time.perf_counter_ns(), self.cycle))
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@classmethod
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def get_loaders(cls) -> typing.Iterable[Type[ProgramLoader]]:
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return [
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AssemblyFileLoader, MemoryImageLoader, ElfBinaryFileLoader
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]
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