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@ -178,10 +178,20 @@ class CPU:
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INS_NOT_IMPLEMENTED(ins)
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INS_NOT_IMPLEMENTED(ins)
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def instruction_beq(self, ins: 'LoadedInstruction'):
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def instruction_beq(self, ins: 'LoadedInstruction'):
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INS_NOT_IMPLEMENTED(ins)
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ASSERT_LEN(ins.args, 3)
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reg1 = ins.get_reg(0)
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reg2 = ins.get_reg(1)
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dest = ins.get_imm(2)
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if self.regs.get(reg1) == self.regs.get(reg2):
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self.pc = dest
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def instruction_bne(self, ins: 'LoadedInstruction'):
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def instruction_bne(self, ins: 'LoadedInstruction'):
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INS_NOT_IMPLEMENTED(ins)
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ASSERT_LEN(ins.args, 3)
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reg1 = ins.get_reg(0)
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reg2 = ins.get_reg(1)
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dest = ins.get_imm(2)
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if self.regs.get(reg1) != self.regs.get(reg2):
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self.pc = dest
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def instruction_blt(self, ins: 'LoadedInstruction'):
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def instruction_blt(self, ins: 'LoadedInstruction'):
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ASSERT_LEN(ins.args, 3)
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ASSERT_LEN(ins.args, 3)
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@ -192,13 +202,28 @@ class CPU:
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self.pc = dest
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self.pc = dest
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def instruction_bge(self, ins: 'LoadedInstruction'):
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def instruction_bge(self, ins: 'LoadedInstruction'):
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INS_NOT_IMPLEMENTED(ins)
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ASSERT_LEN(ins.args, 3)
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reg1 = ins.get_reg(0)
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reg2 = ins.get_reg(1)
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dest = ins.get_imm(2)
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if self.regs.get(reg1) >= self.regs.get(reg2):
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self.pc = dest
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def instruction_bltu(self, ins: 'LoadedInstruction'):
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def instruction_bltu(self, ins: 'LoadedInstruction'):
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INS_NOT_IMPLEMENTED(ins)
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ASSERT_LEN(ins.args, 3)
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reg1 = to_unsigned(ins.get_reg(0))
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reg2 = to_unsigned(ins.get_reg(1))
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dest = ins.get_imm(2)
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if self.regs.get(reg1) < self.regs.get(reg2):
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self.pc = dest
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def instruction_bgeu(self, ins: 'LoadedInstruction'):
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def instruction_bgeu(self, ins: 'LoadedInstruction'):
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INS_NOT_IMPLEMENTED(ins)
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ASSERT_LEN(ins.args, 3)
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reg1 = to_unsigned(ins.get_reg(0))
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reg2 = to_unsigned(ins.get_reg(1))
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dest = ins.get_imm(2)
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if self.regs.get(reg1) >= self.regs.get(reg2):
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self.pc = dest
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def instruction_j(self, ins: 'LoadedInstruction'):
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def instruction_j(self, ins: 'LoadedInstruction'):
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INS_NOT_IMPLEMENTED(ins)
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INS_NOT_IMPLEMENTED(ins)
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