anton/riscemu
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

kernel-mode #1

Manually merged
anton merged 69 commits from kernel-mode into master 2021-11-16 08:02:40 +01:00
Conversation 0 Commits 69 Files Changed 32 +1 -2
1 changed files with 1 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files
Showing only changes of commit c9a136d595 - Show all commits

3
riscemu/instructions/RV32I.py
View File

@ -154,8 +154,7 @@ class RV32I(InstructionSet):
ASSERT_LEN(ins.args, 2)
reg = ins.get_reg(0)
imm = to_unsigned(ins.get_imm(1))
self.pc += (imm << 12)
self.regs.set(reg, self.pc)
self.regs.set(reg, self.pc + (imm << 12))
def instruction_xor(self, ins: 'LoadedInstruction'):
rd, rs1, rs2 = self.parse_rd_rs_rs(ins)