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kernel-mode #1

Manually merged
anton merged 69 commits from kernel-mode into master 2021-11-16 08:02:40 +01:00
Conversation 0 Commits 69 Files Changed 32 +16 -6
3 changed files with 16 additions and 6 deletions
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Showing only changes of commit 3033eb9985 - Show all commits

12
riscemu/priv/ImageLoader.py
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@ -98,7 +98,7 @@ class MemoryImageMMU(PrivMMU):
@lru_cache(maxsize=32) @lru_cache(maxsize=32)
def get_sec_containing(self, addr: int) -> Optional[LoadedMemorySection]: def get_sec_containing(self, addr: int) -> Optional[LoadedMemorySection]:
next_sec = len(self.data) next_sec = len(self.data)
for sec_addr, name in sorted(self.debug_info['sections'].items(), key=lambda x: int(x[0]), reverse=True): for sec_addr, name in reversed(self.debug_info['sections'].items()):
if addr >= int(sec_addr): if addr >= int(sec_addr):
owner, name = name.split(':') owner, name = name.split(':')
base = int(sec_addr) base = int(sec_addr)
@ -107,3 +107,13 @@ class MemoryImageMMU(PrivMMU):
return ElfLoadedMemorySection(name, base, size, self.data[base:next_sec], flags, owner) return ElfLoadedMemorySection(name, base, size, self.data[base:next_sec], flags, owner)
else: else:
next_sec = int(sec_addr) next_sec = int(sec_addr)
def translate_address(self, addr: int):
sec = self.get_sec_containing(addr)
if sec.name == '.empty':
return "<empty>"
symbs = self.debug_info['symbols'][sec.owner]
for sym, val in reversed(symbs.items()):
if addr >= val:
return "{}{:+x} ({}:{})".format(sym, addr - val, sec.owner, sec.name)
return "{}:{}{:+x}".format(sec.owner, sec.name, addr - sec.base)

2
riscemu/priv/PrivMMU.py
View File

@ -19,6 +19,8 @@ class PrivMMU(MMU):
def set_cpu(self, cpu: 'PrivCPU'): def set_cpu(self, cpu: 'PrivCPU'):
self.cpu = cpu self.cpu = cpu
def translate_address(self, addr: int):
return ""
class LoadedElfMMU(PrivMMU): class LoadedElfMMU(PrivMMU):
def __init__(self, elf: ElfExecutable): def __init__(self, elf: ElfExecutable):

8
riscemu/priv/PrivRV32I.py
View File

@ -81,12 +81,10 @@ class PrivRV32I(RV32I):
sec = self.mmu.get_sec_containing(mepc) sec = self.mmu.get_sec_containing(mepc)
if sec is not None: if sec is not None:
print(FMT_CPU + "[CPU] [{}] returning to mode: {} in binary {}, section {}, addr 0x{:x}".format( print(FMT_CPU + "[CPU] [{}] returning to mode {} in {}".format(
self.cpu.cycle, self.cpu.cycle,
PrivModes(mpp), PrivModes(mpp).name,
sec.owner, self.mmu.translate_address(mepc)
sec.name,
mepc
) + FMT_NONE) ) + FMT_NONE)
def instruction_uret(self, ins: 'LoadedInstruction'): def instruction_uret(self, ins: 'LoadedInstruction'):