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No commits in common. '1b26497e4cd61156532b3bf6f6190a6ccfbcae32' and '51d23a16307b7aa50a8e38d6094158468458d257' have entirely different histories.

@ -1,20 +0,0 @@
.data
my_data:
.word 0x11223344, 0x55667788, 0x9900aabb, 0xccddeeff
.text
main:
// load base address into t0
la t0, my_data
// begin loading words and printing them
lw a0, 0(t0)
print.uhex a0
lw a0, 4(t0)
print.uhex a0
lw a0, 8(t0)
print.uhex a0
lw a0, 12(t0)
print.uhex a0
// exit
li a7, 93
ecall

@ -1,4 +1,4 @@
from abc import ABC
from abc import ABC, abstractmethod
from typing import Optional
from riscemu.types import MemorySection, MemoryFlags, T_RelativeAddress
@ -19,4 +19,4 @@ class IOModule(MemorySection, ABC):
def __repr__(self):
return "{}[{}] at 0x{:0X} (size={}bytes, flags={})".format(
self.__class__.__name__, self.name, self.base, self.size, self.flags
)
)

@ -25,4 +25,4 @@ from .parser import tokenize, parse_tokens, AssemblyFileLoader
__author__ = "Anton Lydike <Anton@Lydike.com>"
__copyright__ = "Copyright 2022 Anton Lydike"
__version__ = '2.0.5'
__version__ = '2.0.4'

@ -1,19 +0,0 @@
from .instruction_set import InstructionSet, Instruction
class RV_Debug(InstructionSet):
def instruction_print(self, ins: Instruction):
reg = ins.get_reg(0)
print("register {} contains value {}".format(reg, self.regs.get(reg)))
def instruction_print_uint(self, ins: Instruction):
reg = ins.get_reg(0)
print("register {} contains value {}".format(reg, self.regs.get(reg).unsigned_value))
def instruction_print_hex(self, ins: Instruction):
reg = ins.get_reg(0)
print("register {} contains value {}".format(reg, hex(self.regs.get(reg))))
def instruction_print_uhex(self, ins: Instruction):
reg = ins.get_reg(0)
print("register {} contains value {}".format(reg, hex(self.regs.get(reg).unsigned_value)))

@ -10,8 +10,7 @@ from .instruction_set import InstructionSet, Instruction
from .RV32M import RV32M
from .RV32I import RV32I
from .RV32A import RV32A
from .RV_Debug import RV_Debug
InstructionSetDict = {
v.__name__: v for v in [RV32I, RV32M, RV32A, RV_Debug]
v.__name__: v for v in [RV32I, RV32M, RV32A]
}

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