From f14bd2b98335d8a2f669e80ec3db4d66b6467cee Mon Sep 17 00:00:00 2001 From: Anton Lydike Date: Sat, 5 Jun 2021 16:19:35 +0200 Subject: [PATCH] [PrivCPU, PrivRV32I] fixed bug where ebreaks where missed during debugging --- riscemu/priv/PrivCPU.py | 4 +++- riscemu/priv/PrivRV32I.py | 3 +++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/riscemu/priv/PrivCPU.py b/riscemu/priv/PrivCPU.py index ed5d3db..ef34bf0 100644 --- a/riscemu/priv/PrivCPU.py +++ b/riscemu/priv/PrivCPU.py @@ -18,6 +18,7 @@ if typing.TYPE_CHECKING: from riscemu import Executable, LoadedExecutable, LoadedInstruction from riscemu.instructions.InstructionSet import InstructionSet + class PrivCPU(CPU): """ This is a CPU that has different modes, instruction sets and registers. @@ -84,6 +85,7 @@ class PrivCPU(CPU): print(FMT_CPU + "Program exited with code {}".format(self.exit_code) + FMT_NONE) sys.exit(self.exit_code) elif self.launch_debug: + self.launch_debug = False launch_debug_session(self, self.mmu, self.regs, "Launching debugger:") self._run(verbose) @@ -152,7 +154,7 @@ class PrivCPU(CPU): # implement trap handling! self.pending_traps.append(trap) - def step(self, verbose = True): + def step(self, verbose=True): try: self.cycle += 1 self._timer_step() diff --git a/riscemu/priv/PrivRV32I.py b/riscemu/priv/PrivRV32I.py index 2be49cb..685edf1 100644 --- a/riscemu/priv/PrivRV32I.py +++ b/riscemu/priv/PrivRV32I.py @@ -132,6 +132,9 @@ class PrivRV32I(RV32I): self.regs.set(rd, self.pc) self.pc = rs + imm - 4 + def instruction_sbreak(self, ins: 'LoadedInstruction'): + raise LaunchDebuggerException() + def parse_crs_ins(self, ins: 'LoadedInstruction'): ASSERT_LEN(ins.args, 3) return ins.get_reg(0), ins.get_reg(1), ins.get_imm(2)