anton/riscemu
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

implemented instructions and, or, slt, sltu

Browse Source
This commit is contained in:
Anton Lydike 2021-04-17 23:53:47 +02:00
parent f8e595b46e
commit dd79c11b3b
2 changed files with 32 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

36
riscemu/CPU.py
View File

@ -172,25 +172,53 @@ class CPU:
INS_NOT_IMPLEMENTED(ins)
def instruction_or(self, ins: 'LoadedInstruction'):
INS_NOT_IMPLEMENTED(ins)
ASSERT_LEN(ins.args, 3)
dst = ins.get_reg(0)
src1 = ins.get_reg(1)
src2 = ins.get_reg(2)
self.regs.set(
dst,
self.regs.get(src1) | self.regs.get(src2)
)
def instruction_ori(self, ins: 'LoadedInstruction'):
INS_NOT_IMPLEMENTED(ins)
def instruction_and(self, ins: 'LoadedInstruction'):
INS_NOT_IMPLEMENTED(ins)
ASSERT_LEN(ins.args, 3)
dst = ins.get_reg(0)
src1 = ins.get_reg(1)
src2 = ins.get_reg(2)
self.regs.set(
dst,
self.regs.get(src1) & self.regs.get(src2)
)
def instruction_andi(self, ins: 'LoadedInstruction'):
INS_NOT_IMPLEMENTED(ins)
def instruction_slt(self, ins: 'LoadedInstruction'):
INS_NOT_IMPLEMENTED(ins)
ASSERT_LEN(ins.args, 3)
dst = ins.get_reg(0)
src1 = ins.get_reg(1)
src2 = ins.get_reg(2)
self.regs.set(
dst,
int(self.regs.get(src1) < self.regs.get(src2))
)
def instruction_slti(self, ins: 'LoadedInstruction'):
INS_NOT_IMPLEMENTED(ins)
def instruction_sltu(self, ins: 'LoadedInstruction'):
INS_NOT_IMPLEMENTED(ins)
ASSERT_LEN(ins.args, 3)
dst = ins.get_reg(0)
src1 = ins.get_reg(1)
src2 = ins.get_reg(2)
self.regs.set(
dst,
int(to_unsigned(self.regs.get(src1)) < to_unsigned(self.regs.get(src2)))
)
def instruction_sltiu(self, ins: 'LoadedInstruction'):
INS_NOT_IMPLEMENTED(ins)

0
riscemu/arithmetic.py Normal file
View File