diff --git a/.idea/riscemu.iml b/.idea/riscemu.iml
index a877ef3..9d9f662 100644
--- a/.idea/riscemu.iml
+++ b/.idea/riscemu.iml
@@ -10,7 +10,7 @@
       <excludeFolder url="file://$MODULE_DIR$/riscemu.egg-info" />
       <excludeFolder url="file://$MODULE_DIR$/build" />
     </content>
-    <orderEntry type="jdk" jdkName="Python 3.10 (riscemu)" jdkType="Python SDK" />
+    <orderEntry type="inheritedJdk" />
     <orderEntry type="sourceFolder" forTests="false" />
   </component>
 </module>
\ No newline at end of file
diff --git a/riscemu/IO/IOModule.py b/riscemu/IO/IOModule.py
index 883d00d..ade42c5 100644
--- a/riscemu/IO/IOModule.py
+++ b/riscemu/IO/IOModule.py
@@ -12,8 +12,7 @@ class IOModule(MemorySection, ABC):
         return self.base <= addr < self.base + self.size and \
                self.base <= addr + size <= self.base + self.size
 
-    def dump(self, start: T_RelativeAddress, end: Optional[T_RelativeAddress] = None, fmt: str = 'hex',
-             bytes_per_row: int = 16, rows: int = 10, group: int = 4):
+    def dump(self, *args, **kwargs):
         print(self)
 
     def __repr__(self):
diff --git a/riscemu/MMU.py b/riscemu/MMU.py
index 7f1bee9..1799436 100644
--- a/riscemu/MMU.py
+++ b/riscemu/MMU.py
@@ -94,7 +94,6 @@ class MMU:
         :return: The bytearray at addr
         """
         if isinstance(addr, Int32):
-            breakpoint()
             addr = addr.unsigned_value
         sec = self.get_sec_containing(addr)
         if sec is None: