made instruction methods private to cpu class so not visible from debugger
This commit is contained in:
parent
c3faaaed02
commit
db8cc9b00c
121
riscemu/CPU.py
121
riscemu/CPU.py
@ -51,21 +51,22 @@ class CPU:
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except RiscemuBaseException as ex:
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print(FMT_ERROR + "[CPU] excpetion caught at 0x{:08X}: {}:".format(self.pc-1, ins) + FMT_NONE)
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print(" " + ex.message())
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traceback.print_exception(type(ex), ex, ex.__traceback__)
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#traceback.print_exception(type(ex), ex, ex.__traceback__)
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if self.conf.debug_on_exception:
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launch_debug_session(self, self.mmu, self.regs,
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"Exception encountered, launching debug:".format(self.pc-1))
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print("Program exited with code {}".format(self.exit_code))
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print(FMT_CPU + "Program exited with code {}".format(self.exit_code) + FMT_NONE)
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def __run_instruction(self, ins: 'LoadedInstruction'):
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name = 'instruction_' + ins.name
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name = '_CPU__instruction_' + ins.name
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if hasattr(self, name):
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getattr(self, name)(ins)
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else:
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# this should never be reached, as unknown instructions are imparsable
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raise RuntimeError("Unknown instruction: {}".format(ins))
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def parse_mem_ins(self, ins: 'LoadedInstruction') -> Tuple[str, int]:
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def __parse_mem_ins(self, ins: 'LoadedInstruction') -> Tuple[str, int]:
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"""
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parses both rd, rs1, imm and rd, imm(rs1) arguments and returns (rd, imm+rs1)
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(so a register and address tuple for memory instructions)
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@ -82,39 +83,39 @@ class CPU:
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rd = ins.get_reg(0)
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return rd, self.regs.get(rs1) + imm
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def instruction_lb(self, ins: 'LoadedInstruction'):
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rd, addr = self.parse_mem_ins(ins)
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def __instruction_lb(self, ins: 'LoadedInstruction'):
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rd, addr = self.__parse_mem_ins(ins)
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self.regs.set(rd, int_from_bytes(self.mmu.read(addr, 1)))
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def instruction_lh(self, ins: 'LoadedInstruction'):
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rd, addr = self.parse_mem_ins(ins)
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def __instruction_lh(self, ins: 'LoadedInstruction'):
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rd, addr = self.__parse_mem_ins(ins)
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self.regs.set(rd, int_from_bytes(self.mmu.read(addr, 2)))
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def instruction_lw(self, ins: 'LoadedInstruction'):
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rd, addr = self.parse_mem_ins(ins)
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def __instruction_lw(self, ins: 'LoadedInstruction'):
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rd, addr = self.__parse_mem_ins(ins)
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self.regs.set(rd, int_from_bytes(self.mmu.read(addr, 4)))
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def instruction_lbu(self, ins: 'LoadedInstruction'):
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rd, addr = self.parse_mem_ins(ins)
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def __instruction_lbu(self, ins: 'LoadedInstruction'):
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rd, addr = self.__parse_mem_ins(ins)
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self.regs.set(rd, int_from_bytes(self.mmu.read(addr, 1), unsigned=True))
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def instruction_lhu(self, ins: 'LoadedInstruction'):
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rd, addr = self.parse_mem_ins(ins)
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def __instruction_lhu(self, ins: 'LoadedInstruction'):
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rd, addr = self.__parse_mem_ins(ins)
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self.regs.set(rd, int_from_bytes(self.mmu.read(addr, 2), unsigned=True))
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def instruction_sb(self, ins: 'LoadedInstruction'):
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rd, addr = self.parse_mem_ins(ins)
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def __instruction_sb(self, ins: 'LoadedInstruction'):
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rd, addr = self.__parse_mem_ins(ins)
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self.mmu.write(addr, 1, int_to_bytes(self.regs.get(rd), 1))
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def instruction_sh(self, ins: 'LoadedInstruction'):
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rd, addr = self.parse_mem_ins(ins)
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def __instruction_sh(self, ins: 'LoadedInstruction'):
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rd, addr = self.__parse_mem_ins(ins)
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self.mmu.write(addr, 2, int_to_bytes(self.regs.get(rd), 2))
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def instruction_sw(self, ins: 'LoadedInstruction'):
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rd, addr = self.parse_mem_ins(ins)
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def __instruction_sw(self, ins: 'LoadedInstruction'):
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rd, addr = self.__parse_mem_ins(ins)
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self.mmu.write(addr, 4, int_to_bytes(self.regs.get(rd), 4))
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def instruction_sll(self, ins: 'LoadedInstruction'):
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def __instruction_sll(self, ins: 'LoadedInstruction'):
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ASSERT_LEN(ins.args, 3)
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dst = ins.get_reg(0)
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src1 = ins.get_reg(1)
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@ -124,7 +125,7 @@ class CPU:
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to_signed(to_unsigned(self.regs.get(src1)) << (self.regs.get(src2) & 0b11111))
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)
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def instruction_slli(self, ins: 'LoadedInstruction'):
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def __instruction_slli(self, ins: 'LoadedInstruction'):
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ASSERT_LEN(ins.args, 3)
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dst = ins.get_reg(0)
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src1 = ins.get_reg(1)
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@ -134,7 +135,7 @@ class CPU:
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to_signed(to_unsigned(self.regs.get(src1)) << (imm & 0b11111))
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)
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def instruction_srl(self, ins: 'LoadedInstruction'):
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def __instruction_srl(self, ins: 'LoadedInstruction'):
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ASSERT_LEN(ins.args, 3)
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dst = ins.get_reg(0)
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src1 = ins.get_reg(1)
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@ -144,7 +145,7 @@ class CPU:
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to_signed(to_unsigned(self.regs.get(src1)) >> (self.regs.get(src2) & 0b11111))
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)
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def instruction_srli(self, ins: 'LoadedInstruction'):
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def __instruction_srli(self, ins: 'LoadedInstruction'):
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ASSERT_LEN(ins.args, 3)
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dst = ins.get_reg(0)
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src1 = ins.get_reg(1)
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@ -154,7 +155,7 @@ class CPU:
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to_signed(to_unsigned(self.regs.get(src1)) >> (imm & 0b11111))
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)
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def instruction_sra(self, ins: 'LoadedInstruction'):
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def __instruction_sra(self, ins: 'LoadedInstruction'):
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ASSERT_LEN(ins.args, 3)
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dst = ins.get_reg(0)
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src1 = ins.get_reg(1)
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@ -164,7 +165,7 @@ class CPU:
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self.regs.get(src1) >> (self.regs.get(src2) & 0b11111)
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)
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def instruction_srai(self, ins: 'LoadedInstruction'):
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def __instruction_srai(self, ins: 'LoadedInstruction'):
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ASSERT_LEN(ins.args, 3)
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dst = ins.get_reg(0)
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src1 = ins.get_reg(1)
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@ -174,7 +175,7 @@ class CPU:
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self.regs.get(src1) >> (imm & 0b11111)
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)
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def instruction_add(self, ins: 'LoadedInstruction'):
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def __instruction_add(self, ins: 'LoadedInstruction'):
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ASSERT_LEN(ins.args, 3)
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dst = ins.get_reg(0)
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src1 = ins.get_reg(1)
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@ -184,7 +185,7 @@ class CPU:
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self.regs.get(src1) + self.regs.get(src2)
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)
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def instruction_addi(self, ins: 'LoadedInstruction'):
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def __instruction_addi(self, ins: 'LoadedInstruction'):
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ASSERT_LEN(ins.args, 3)
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dst = ins.get_reg(0)
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src1 = ins.get_reg(1)
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@ -194,7 +195,7 @@ class CPU:
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self.regs.get(src1) + imm
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)
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def instruction_sub(self, ins: 'LoadedInstruction'):
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def __instruction_sub(self, ins: 'LoadedInstruction'):
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ASSERT_LEN(ins.args, 3)
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dst = ins.get_reg(0)
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src1 = ins.get_reg(1)
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@ -204,13 +205,13 @@ class CPU:
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self.regs.get(src1) - self.regs.get(src2)
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)
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def instruction_lui(self, ins: 'LoadedInstruction'):
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def __instruction_lui(self, ins: 'LoadedInstruction'):
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INS_NOT_IMPLEMENTED(ins)
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def instruction_auipc(self, ins: 'LoadedInstruction'):
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def __instruction_auipc(self, ins: 'LoadedInstruction'):
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INS_NOT_IMPLEMENTED(ins)
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def instruction_xor(self, ins: 'LoadedInstruction'):
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def __instruction_xor(self, ins: 'LoadedInstruction'):
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ASSERT_LEN(ins.args, 3)
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dst = ins.get_reg(0)
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src1 = ins.get_reg(1)
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@ -220,10 +221,10 @@ class CPU:
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self.regs.get(src1) ^ self.regs.get(src2)
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)
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def instruction_xori(self, ins: 'LoadedInstruction'):
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def __instruction_xori(self, ins: 'LoadedInstruction'):
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INS_NOT_IMPLEMENTED(ins)
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def instruction_or(self, ins: 'LoadedInstruction'):
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def __instruction_or(self, ins: 'LoadedInstruction'):
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ASSERT_LEN(ins.args, 3)
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dst = ins.get_reg(0)
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src1 = ins.get_reg(1)
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@ -233,10 +234,10 @@ class CPU:
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self.regs.get(src1) | self.regs.get(src2)
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)
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def instruction_ori(self, ins: 'LoadedInstruction'):
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def __instruction_ori(self, ins: 'LoadedInstruction'):
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INS_NOT_IMPLEMENTED(ins)
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def instruction_and(self, ins: 'LoadedInstruction'):
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def __instruction_and(self, ins: 'LoadedInstruction'):
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ASSERT_LEN(ins.args, 3)
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dst = ins.get_reg(0)
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src1 = ins.get_reg(1)
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@ -246,10 +247,10 @@ class CPU:
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self.regs.get(src1) & self.regs.get(src2)
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)
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def instruction_andi(self, ins: 'LoadedInstruction'):
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def __instruction_andi(self, ins: 'LoadedInstruction'):
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INS_NOT_IMPLEMENTED(ins)
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def instruction_slt(self, ins: 'LoadedInstruction'):
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def __instruction_slt(self, ins: 'LoadedInstruction'):
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ASSERT_LEN(ins.args, 3)
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dst = ins.get_reg(0)
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src1 = ins.get_reg(1)
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@ -259,10 +260,10 @@ class CPU:
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int(self.regs.get(src1) < self.regs.get(src2))
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)
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def instruction_slti(self, ins: 'LoadedInstruction'):
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def __instruction_slti(self, ins: 'LoadedInstruction'):
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INS_NOT_IMPLEMENTED(ins)
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def instruction_sltu(self, ins: 'LoadedInstruction'):
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def __instruction_sltu(self, ins: 'LoadedInstruction'):
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ASSERT_LEN(ins.args, 3)
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dst = ins.get_reg(0)
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src1 = ins.get_reg(1)
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@ -272,10 +273,10 @@ class CPU:
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int(to_unsigned(self.regs.get(src1)) < to_unsigned(self.regs.get(src2)))
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)
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def instruction_sltiu(self, ins: 'LoadedInstruction'):
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def __instruction_sltiu(self, ins: 'LoadedInstruction'):
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INS_NOT_IMPLEMENTED(ins)
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def instruction_beq(self, ins: 'LoadedInstruction'):
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def __instruction_beq(self, ins: 'LoadedInstruction'):
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ASSERT_LEN(ins.args, 3)
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reg1 = ins.get_reg(0)
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reg2 = ins.get_reg(1)
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@ -283,7 +284,7 @@ class CPU:
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if self.regs.get(reg1) == self.regs.get(reg2):
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self.pc = dest
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def instruction_bne(self, ins: 'LoadedInstruction'):
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def __instruction_bne(self, ins: 'LoadedInstruction'):
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ASSERT_LEN(ins.args, 3)
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reg1 = ins.get_reg(0)
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reg2 = ins.get_reg(1)
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@ -291,7 +292,7 @@ class CPU:
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if self.regs.get(reg1) != self.regs.get(reg2):
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self.pc = dest
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def instruction_blt(self, ins: 'LoadedInstruction'):
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def __instruction_blt(self, ins: 'LoadedInstruction'):
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ASSERT_LEN(ins.args, 3)
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reg1 = ins.get_reg(0)
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reg2 = ins.get_reg(1)
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@ -299,7 +300,7 @@ class CPU:
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if self.regs.get(reg1) < self.regs.get(reg2):
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self.pc = dest
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def instruction_bge(self, ins: 'LoadedInstruction'):
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def __instruction_bge(self, ins: 'LoadedInstruction'):
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ASSERT_LEN(ins.args, 3)
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reg1 = ins.get_reg(0)
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reg2 = ins.get_reg(1)
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@ -307,7 +308,7 @@ class CPU:
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if self.regs.get(reg1) >= self.regs.get(reg2):
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self.pc = dest
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def instruction_bltu(self, ins: 'LoadedInstruction'):
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def __instruction_bltu(self, ins: 'LoadedInstruction'):
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ASSERT_LEN(ins.args, 3)
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reg1 = to_unsigned(ins.get_reg(0))
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reg2 = to_unsigned(ins.get_reg(1))
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@ -315,7 +316,7 @@ class CPU:
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if self.regs.get(reg1) < self.regs.get(reg2):
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self.pc = dest
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def instruction_bgeu(self, ins: 'LoadedInstruction'):
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def __instruction_bgeu(self, ins: 'LoadedInstruction'):
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ASSERT_LEN(ins.args, 3)
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reg1 = to_unsigned(ins.get_reg(0))
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reg2 = to_unsigned(ins.get_reg(1))
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@ -323,12 +324,12 @@ class CPU:
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if self.regs.get(reg1) >= self.regs.get(reg2):
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self.pc = dest
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def instruction_j(self, ins: 'LoadedInstruction'):
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def __instruction_j(self, ins: 'LoadedInstruction'):
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ASSERT_LEN(ins.args, 1)
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addr = ins.get_imm(0)
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self.pc = addr
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def instruction_jal(self, ins: 'LoadedInstruction'):
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def __instruction_jal(self, ins: 'LoadedInstruction'):
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reg = 'ra' # default register is ra
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if len(ins.args) == 1:
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addr = ins.get_imm(0)
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@ -339,39 +340,39 @@ class CPU:
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self.regs.set(reg, self.pc)
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self.pc = addr
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def instruction_jalr(self, ins: 'LoadedInstruction'):
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def __instruction_jalr(self, ins: 'LoadedInstruction'):
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ASSERT_LEN(ins.args, 2)
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reg = ins.get_reg(0)
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addr = ins.get_imm(1)
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self.regs.set(reg, self.pc)
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self.pc = addr
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def instruction_ret(self, ins: 'LoadedInstruction'):
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def __instruction_ret(self, ins: 'LoadedInstruction'):
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ASSERT_LEN(ins.args, 0)
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self.pc = self.regs.get('ra')
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def instruction_ecall(self, ins: 'LoadedInstruction'):
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self.instruction_scall(ins)
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def __instruction_ecall(self, ins: 'LoadedInstruction'):
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self.__instruction_scall(ins)
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def instruction_ebreak(self, ins: 'LoadedInstruction'):
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self.instruction_sbreak(ins)
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def __instruction_ebreak(self, ins: 'LoadedInstruction'):
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self.__instruction_sbreak(ins)
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def instruction_scall(self, ins: 'LoadedInstruction'):
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def __instruction_scall(self, ins: 'LoadedInstruction'):
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ASSERT_LEN(ins.args, 0)
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syscall = Syscall(self.regs.get('a7'), self.regs, self)
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self.syscall_int.handle_syscall(syscall)
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def instruction_sbreak(self, ins: 'LoadedInstruction'):
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def __instruction_sbreak(self, ins: 'LoadedInstruction'):
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launch_debug_session(self, self.mmu, self.regs, "Debug instruction encountered at 0x{:08X}".format(self.pc))
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def instruction_nop(self, ins: 'LoadedInstruction'):
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def __instruction_nop(self, ins: 'LoadedInstruction'):
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pass
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@staticmethod
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def all_instructions():
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for method in vars(CPU):
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if method.startswith('instruction_'):
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yield method[12:]
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if method.startswith('_CPU__instruction_'):
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yield method[18:]
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def __repr__(self):
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return "CPU(pc=0x{:08X}, cycle={})".format(
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