From d56dca3ff418b8f2bddbbace2c6759d84b581560 Mon Sep 17 00:00:00 2001
From: Anton Lydike <anton@lydike.com>
Date: Sun, 18 Apr 2021 09:32:37 +0200
Subject: [PATCH] added better debugging environment

---
 riscemu/CPU.py    | 18 ++++++------------
 riscemu/Config.py |  2 ++
 riscemu/debug.py  | 23 +++++++++++++++++++++++
 3 files changed, 31 insertions(+), 12 deletions(-)
 create mode 100644 riscemu/debug.py

diff --git a/riscemu/CPU.py b/riscemu/CPU.py
index 86ed14a..0abc740 100644
--- a/riscemu/CPU.py
+++ b/riscemu/CPU.py
@@ -6,6 +6,7 @@ from .helpers import *
 from .Config import RunConfig
 from .Registers import Registers
 from .Syscall import SyscallInterface, Syscall
+from .debug import launch_debug_session
 
 import typing
 
@@ -48,9 +49,12 @@ class CPU:
                 self.pc += 1
                 self.__run_instruction(ins)
         except RiscemuBaseException as ex:
-            print(FMT_ERROR + "[CPU] excpetion caught at {}:".format(ins) + FMT_NONE)
+            print(FMT_ERROR + "[CPU] excpetion caught at 0x{:08X}: {}:".format(self.pc-1, ins) + FMT_NONE)
             print("      " + ex.message())
             traceback.print_exception(type(ex), ex, ex.__traceback__)
+            if self.conf.debug_on_exception:
+                launch_debug_session(self, self.mmu, self.regs,
+                                     "Exception encountered, launching debug:".format(self.pc-1))
 
         print("Program exited with code {}".format(self.exit_code))
 
@@ -358,17 +362,7 @@ class CPU:
         self.syscall_int.handle_syscall(syscall)
 
     def instruction_sbreak(self, ins: 'LoadedInstruction'):
-        if self.conf.debug_instruction:
-            import code
-            import readline
-            import rlcompleter
-
-            vars = globals()
-            vars.update(locals())
-
-            readline.set_completer(rlcompleter.Completer(vars).complete)
-            readline.parse_and_bind("tab: complete")
-            code.InteractiveConsole(vars).interact()
+        launch_debug_session(self, self.mmu, self.regs, "Debug instruction encountered at 0x{:08X}".format(self.pc))
 
     def instruction_nop(self, ins: 'LoadedInstruction'):
         pass
diff --git a/riscemu/Config.py b/riscemu/Config.py
index 6cd34e4..e5ad0a6 100644
--- a/riscemu/Config.py
+++ b/riscemu/Config.py
@@ -6,7 +6,9 @@ from typing import Optional
 class RunConfig:
     color: bool = True
     preffered_stack_size: Optional[int] = None
+    # debugging
     debug_instruction: bool = True
+    debug_on_exception = True
     # allowed syscalls
     scall_input: bool = True
     scall_fs: bool = False
diff --git a/riscemu/debug.py b/riscemu/debug.py
new file mode 100644
index 0000000..2d93ccc
--- /dev/null
+++ b/riscemu/debug.py
@@ -0,0 +1,23 @@
+import typing
+if typing.TYPE_CHECKING:
+    from . import *
+
+
+def launch_debug_session(cpu: 'CPU', mmu: 'MMU', reg: 'Registers', prompt=""):
+    if not cpu.conf.debug_instruction:
+        return
+    import code
+    import readline
+    import rlcompleter
+
+    # setup some aliases
+    registers = reg
+    memory = mmu
+    mem = mmu
+
+    vars = globals()
+    vars.update(locals())
+
+    readline.set_completer(rlcompleter.Completer(vars).complete)
+    readline.parse_and_bind("tab: complete")
+    code.InteractiveConsole(vars).interact(banner=prompt, exitmsg="Resuming simulation")