From c963fe39896fb12e1dbad2833b34dfa9bfa56617 Mon Sep 17 00:00:00 2001
From: Anton Lydike <anton@lydike.com>
Date: Wed, 26 May 2021 18:40:42 +0200
Subject: [PATCH] [Priv] small fixes for overlooked things

---
 riscemu/priv/CSR.py       | 5 ++++-
 riscemu/priv/PrivCPU.py   | 3 ++-
 riscemu/priv/PrivRV32I.py | 1 -
 3 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/riscemu/priv/CSR.py b/riscemu/priv/CSR.py
index 32bbb97..b7b007e 100644
--- a/riscemu/priv/CSR.py
+++ b/riscemu/priv/CSR.py
@@ -2,6 +2,7 @@ from typing import Dict, Union, Callable, Optional
 from collections import defaultdict
 from .privmodes import PrivModes
 from .Exceptions import IllegalInstructionTrap
+from ..helpers import to_unsigned
 
 MSTATUS_OFFSETS = {
     'uie': 0,
@@ -74,12 +75,14 @@ class CSR:
     def __init__(self):
         self.regs = defaultdict(lambda: 0)
         self.listeners = defaultdict(lambda: (lambda x, y: None))
+        self.virtual_regs = dict()
         #TODO: implement write masks (bitmasks which control writeable bits in registers
 
     def set(self, addr: Union[str, int], val: int):
         addr = self._addr_to_name(addr)
         if addr is None:
             return
+        val = to_unsigned(val)
         self.listeners[addr](self.regs[addr], val)
         self.regs[addr] = val
 
@@ -135,7 +138,7 @@ class CSR:
             raise IllegalInstructionTrap()
 
     def assert_can_write(self, mode: PrivModes, addr: int):
-        if (addr >> 8) & 3 > mode.value() or addr >> 10 == 11:
+        if (addr >> 8) & 3 > mode.value or addr >> 10 == 11:
             raise IllegalInstructionTrap()
 
     def _addr_to_name(self, addr: Union[str, int]) -> Optional[int]:
diff --git a/riscemu/priv/PrivCPU.py b/riscemu/priv/PrivCPU.py
index 6654b92..fe0df86 100644
--- a/riscemu/priv/PrivCPU.py
+++ b/riscemu/priv/PrivCPU.py
@@ -69,10 +69,11 @@ class PrivCPU(CPU):
         ins = None
         try:
             while not self.exit:
-                self.step(verbose=False)
+                self.step(verbose)
         except RiscemuBaseException as ex:
             if isinstance(ex, LaunchDebuggerException):
                 self.launch_debug = True
+                self.pc += self.INS_XLEN
             else:
                 print(FMT_ERROR + "[CPU] excpetion caught at 0x{:08X}: {}:".format(self.pc - 1, ins) + FMT_NONE)
                 print(ex.message())
diff --git a/riscemu/priv/PrivRV32I.py b/riscemu/priv/PrivRV32I.py
index f0b5c23..1c17791 100644
--- a/riscemu/priv/PrivRV32I.py
+++ b/riscemu/priv/PrivRV32I.py
@@ -130,5 +130,4 @@ class PrivRV32I(RV32I):
 
     def parse_mem_ins(self, ins: 'LoadedInstruction') -> Tuple[str, int]:
         ASSERT_LEN(ins.args, 3)
-        print("dop")
         return ins.get_reg(1), self.get_reg_content(ins, 0) + ins.get_imm(2)