From c7e14a3b4204b95262532aca563b8944247c64ab Mon Sep 17 00:00:00 2001
From: Anton Lydike <me@antonlydike.de>
Date: Mon, 29 May 2023 11:26:26 +0100
Subject: [PATCH] misc: annotations and dead code removal

---
 CHANGELOG.md         | 16 ++++++++++++++++
 riscemu/MMU.py       | 11 -----------
 riscemu/types/cpu.py |  2 +-
 3 files changed, 17 insertions(+), 12 deletions(-)

diff --git a/CHANGELOG.md b/CHANGELOG.md
index 8075127..bf42c94 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -1,5 +1,21 @@
 # Changelog
 
+## Upcoming 2.0.6
+
+**Planned:**
+ - Add a floating point unit
+ - Add a crt0.s
+ - Add `mmap2` syscall with code 192
+
+## 2.0.5
+
+ - Added unlimited register mode with `-o unlimited_regs`
+
+## 2.0.4
+
+ - Bugfix: fix a sign issue in instruction parsing for `rd, rs, rs` format
+ - Bugfix: respect `conf.debug_instruction` setting
+
 ## 2.0.3 - 2022-04-18
 
  - Syscalls: cleaned up formatting and added instructions for extensions
diff --git a/riscemu/MMU.py b/riscemu/MMU.py
index 8bb79aa..93f7612 100644
--- a/riscemu/MMU.py
+++ b/riscemu/MMU.py
@@ -347,14 +347,3 @@ class MMU:
             return sec.context
 
         return InstructionContext()
-
-    def report_addr(self, addr: T_AbsoluteAddress):
-        sec = self.get_sec_containing(addr)
-        if not sec:
-            print("addr is in no section!")
-            return
-        owner = [b for b in self.programs if b.name == sec.owner]
-        if owner:
-            print("owned by: {}".format(owner[0]))
-
-        print("{}: 0x{:0x} + 0x{:0x}".format(name, val, addr - val))
diff --git a/riscemu/types/cpu.py b/riscemu/types/cpu.py
index 8ee8b6d..5a1fc21 100644
--- a/riscemu/types/cpu.py
+++ b/riscemu/types/cpu.py
@@ -1,6 +1,6 @@
 import typing
 from abc import ABC, abstractmethod
-from typing import List, Type, Callable, Set, Dict
+from typing import List, Type, Callable, Set, Dict, TYPE_CHECKING
 
 from ..registers import Registers
 from ..config import RunConfig