diff --git a/.idea/misc.xml b/.idea/misc.xml
index b0653d7..a15ea67 100644
--- a/.idea/misc.xml
+++ b/.idea/misc.xml
@@ -1,4 +1,4 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <project version="4">
-  <component name="ProjectRootManager" version="2" project-jdk-name="Python 3.10 (riscemu)" project-jdk-type="Python SDK" />
+  <component name="ProjectRootManager" version="2" project-jdk-name="Python 3.8 (riscemu)" project-jdk-type="Python SDK" />
 </project>
\ No newline at end of file
diff --git a/.idea/riscemu.iml b/.idea/riscemu.iml
index a877ef3..9d9f662 100644
--- a/.idea/riscemu.iml
+++ b/.idea/riscemu.iml
@@ -10,7 +10,7 @@
       <excludeFolder url="file://$MODULE_DIR$/riscemu.egg-info" />
       <excludeFolder url="file://$MODULE_DIR$/build" />
     </content>
-    <orderEntry type="jdk" jdkName="Python 3.10 (riscemu)" jdkType="Python SDK" />
+    <orderEntry type="inheritedJdk" />
     <orderEntry type="sourceFolder" forTests="false" />
   </component>
 </module>
\ No newline at end of file
diff --git a/CHANGELOG.md b/CHANGELOG.md
index 327de90..df712fb 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -1,5 +1,21 @@
 # Changelog
 
+## Upcoming 2.0.6
+
+**Planned:**
+ - Add a floating point unit
+ - Add a crt0.s
+ - Add `mmap2` syscall with code 192
+
+## 2.0.5
+
+ - Added unlimited register mode with `-o unlimited_regs`
+
+## 2.0.4
+
+ - Bugfix: fix a sign issue in instruction parsing for `rd, rs, rs` format
+ - Bugfix: respect `conf.debug_instruction` setting
+
 ## 2.0.3 - 2022-04-18
 
  - Syscalls: cleaned up formatting and added instructions for extensions
diff --git a/riscemu/MMU.py b/riscemu/MMU.py
index 7f1bee9..24cab4e 100644
--- a/riscemu/MMU.py
+++ b/riscemu/MMU.py
@@ -252,7 +252,7 @@ class MMU:
             sec.base = at_addr
             self.sections.append(sec)
             self._update_state()
-            return True
+        return True
 
     def _update_state(self):
         """
@@ -281,14 +281,3 @@ class MMU:
             return sec.context
 
         return InstructionContext()
-
-    def report_addr(self, addr: T_AbsoluteAddress):
-        sec = self.get_sec_containing(addr)
-        if not sec:
-            print("addr is in no section!")
-            return
-        owner = [b for b in self.programs if b.name == sec.owner]
-        if owner:
-            print("owned by: {}".format(owner[0]))
-
-        print("{}: 0x{:0x} + 0x{:0x}".format(name, val, addr - val))
diff --git a/riscemu/types/cpu.py b/riscemu/types/cpu.py
index 4672f0c..0ee0ebd 100644
--- a/riscemu/types/cpu.py
+++ b/riscemu/types/cpu.py
@@ -1,12 +1,16 @@
 import typing
 from abc import ABC, abstractmethod
-from typing import List, Type, Callable, Set, Dict
+from typing import List, Type, Callable, Set, Dict, TYPE_CHECKING
 
 from ..registers import Registers
 from ..config import RunConfig
 from ..colors import FMT_RED, FMT_NONE, FMT_ERROR, FMT_CPU
 from . import T_AbsoluteAddress, Instruction, Program, ProgramLoader
 
+if TYPE_CHECKING:
+    from .. import MMU
+    from ..instructions import InstructionSet
+
 
 class CPU(ABC):
     # static cpu configuration