From a51681811fffddaa076e68b891ff593f69ca18b0 Mon Sep 17 00:00:00 2001
From: Anton Lydike <me@antonlydike.de>
Date: Mon, 1 May 2023 16:57:49 +0100
Subject: [PATCH] fix ci (pt2) ?

---
 .github/workflows/jupyterlite.yml              | 16 +++++++---------
 .idea/inspectionProfiles/profiles_settings.xml |  2 +-
 .idea/misc.xml                                 |  2 +-
 .idea/modules.xml                              |  2 +-
 .idea/riscemu.iml                              |  2 +-
 .idea/vcs.xml                                  |  2 +-
 CHANGELOG.md                                   |  4 ++--
 LICENSE                                        |  2 +-
 README.md                                      | 15 +++++++--------
 docs/assembly.md                               |  4 ++--
 docs/debugging.md                              |  8 ++++----
 docs/internal-structure.md                     |  7 +++----
 docs/libraries.md                              |  1 -
 docs/syscalls.md                               |  4 ++--
 examples/lib/libstring.asm                     |  2 --
 examples/static-data.asm                       |  2 +-
 generate-docs.sh                               |  2 +-
 project.toml                                   |  1 -
 requirements-dev.txt                           |  3 +++
 riscemu/priv/Exceptions.py                     |  2 +-
 riscemu/syscall.py                             |  2 +-
 riscemu/types/instruction_context.py           |  4 ++--
 sphinx-docs/.gitignore                         |  2 +-
 sphinx-docs/source/index.rst                   |  2 +-
 24 files changed, 44 insertions(+), 49 deletions(-)
 create mode 100644 requirements-dev.txt

diff --git a/.github/workflows/jupyterlite.yml b/.github/workflows/jupyterlite.yml
index 421f48c..f7036d6 100644
--- a/.github/workflows/jupyterlite.yml
+++ b/.github/workflows/jupyterlite.yml
@@ -27,7 +27,7 @@ jobs:
       - name: Install dependencies
         run: |
           python -m pip install jupyterlite[all] libarchive-c build pyodide-build
-          
+
       - name: Build RiscEmu source distribution
         run: |
           cd riscemu
@@ -42,7 +42,7 @@ jobs:
         with:
           path: pyodide
           key: pyodide
-          
+
       - name: Clone pyodide if not cached
         if: steps.cache-pyodide.outputs.cache-hit != 'true'
         run: git clone https://github.com/pyodide/pyodide.git
@@ -51,16 +51,16 @@ jobs:
       # and do the necessary updates before building.
       - name: Build custom Pyodide distribution
         run: |
-          
+
           cd pyodide
           git fetch --all
           git checkout 0.22.0a3
           python -m pip install -r requirements.txt
           sudo apt update && sudo apt install f2c
-          
+
           rm -rf packages/riscemu
           pyodide skeleton pypi riscemu
-          
+
           PYODIDE_PACKAGES="riscemu" make
 
       - name: Build the JupyterLite site
@@ -68,11 +68,11 @@ jobs:
           mkdir content
           cp riscemu/docs/* content -r
           cp riscemu/examples content -r
-          
+
           rm -rf pyodide/pyodide
           mkdir pyodide/pyodide
           mv pyodide/dist pyodide/pyodide/pyodide
-          
+
           python -m jupyter lite build --contents content --pyodide pyodide/pyodide
 
       - name: Upload artifact
@@ -96,5 +96,3 @@ jobs:
       - name: Deploy to GitHub Pages
         id: deployment
         uses: actions/deploy-pages@v1
-
-
diff --git a/.idea/inspectionProfiles/profiles_settings.xml b/.idea/inspectionProfiles/profiles_settings.xml
index 105ce2d..cc5462d 100644
--- a/.idea/inspectionProfiles/profiles_settings.xml
+++ b/.idea/inspectionProfiles/profiles_settings.xml
@@ -3,4 +3,4 @@
     <option name="USE_PROJECT_PROFILE" value="false" />
     <version value="1.0" />
   </settings>
-</component>
\ No newline at end of file
+</component>
diff --git a/.idea/misc.xml b/.idea/misc.xml
index b0653d7..3d5f5f4 100644
--- a/.idea/misc.xml
+++ b/.idea/misc.xml
@@ -1,4 +1,4 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <project version="4">
   <component name="ProjectRootManager" version="2" project-jdk-name="Python 3.10 (riscemu)" project-jdk-type="Python SDK" />
-</project>
\ No newline at end of file
+</project>
diff --git a/.idea/modules.xml b/.idea/modules.xml
index a40226d..291ef1e 100644
--- a/.idea/modules.xml
+++ b/.idea/modules.xml
@@ -5,4 +5,4 @@
       <module fileurl="file://$PROJECT_DIR$/.idea/riscemu.iml" filepath="$PROJECT_DIR$/.idea/riscemu.iml" />
     </modules>
   </component>
-</project>
\ No newline at end of file
+</project>
diff --git a/.idea/riscemu.iml b/.idea/riscemu.iml
index 9d9f662..9f548db 100644
--- a/.idea/riscemu.iml
+++ b/.idea/riscemu.iml
@@ -13,4 +13,4 @@
     <orderEntry type="inheritedJdk" />
     <orderEntry type="sourceFolder" forTests="false" />
   </component>
-</module>
\ No newline at end of file
+</module>
diff --git a/.idea/vcs.xml b/.idea/vcs.xml
index 94a25f7..5ace414 100644
--- a/.idea/vcs.xml
+++ b/.idea/vcs.xml
@@ -3,4 +3,4 @@
   <component name="VcsDirectoryMappings">
     <mapping directory="$PROJECT_DIR$" vcs="Git" />
   </component>
-</project>
\ No newline at end of file
+</project>
diff --git a/CHANGELOG.md b/CHANGELOG.md
index 327de90..8075127 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -9,7 +9,7 @@
  - Fixed bug where wrong parts of section would be printed in mmu.dump()
  - Removed tests for bind_twos_complement as the function is now redundant with the introduction of Int32
  - Fixed address translation error for sections without symbols
- - Changed verbosity level at which start and end of CPU are printed, added prints for start and stack loading 
+ - Changed verbosity level at which start and end of CPU are printed, added prints for start and stack loading
 
 ## 2.0.2
 
@@ -23,6 +23,6 @@
 
 ## 2.0.0
 
- - Correct handling of 32 bit overflows and underflows 
+ - Correct handling of 32 bit overflows and underflows
  - Complete revamp of internal data structures
  - Completely reworked how assembly is parsed
diff --git a/LICENSE b/LICENSE
index c650be9..4aebac3 100644
--- a/LICENSE
+++ b/LICENSE
@@ -18,4 +18,4 @@ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
 AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-SOFTWARE.
\ No newline at end of file
+SOFTWARE.
diff --git a/README.md b/README.md
index ac0bb5b..258eb11 100644
--- a/README.md
+++ b/README.md
@@ -10,7 +10,7 @@ This emulator contains:
 * RISC-V Assembly loader
 * Emulation for most parts of the basic RISC-V instruction set and the M and A extensions
 * Naive memory emulator
-* Basic implementation of some syscalls 
+* Basic implementation of some syscalls
 * A debugging environment
 
 ## Installation:
@@ -33,7 +33,7 @@ Program exited with code 0
 
 If you want to run it from a python script, here is [an online demo](https://AntonLydike.github.io/riscemu/lab/index.html?path=PythonDemo.ipynb).
 
-The [`read` syscall](docs/syscalls.md) defaults to readline behaviour. Reading "true chunks" (ignoring newlines) is currently not supported.  
+The [`read` syscall](docs/syscalls.md) defaults to readline behaviour. Reading "true chunks" (ignoring newlines) is currently not supported.
 
 See the docs on [asembly](docs/assembly.md) for more detail on how to write assembly code for this emulator.
 See the [list of implemented syscalls](docs/syscalls.md) for more details on how to syscall.
@@ -71,10 +71,10 @@ disable_io              Disallow reading/writing from stdin/stdout/stderr
 --instruction-sets INSTRUCTION_SETS: (-is)
                         A list of comma separated instruction sets you want to load:
                         Currently implemented: RV32I, RV32M
-``` 
+```
 
-If multiple files are specified, all are loaded into memeory, but only the last one is executed. This might be improved 
-later, maybe the `_init` section of each binary is executed before the main loop starts? 
+If multiple files are specified, all are loaded into memeory, but only the last one is executed. This might be improved
+later, maybe the `_init` section of each binary is executed before the main loop starts?
 
 If `stack_size` is greater than zero, a stack is allocated and initialized, with the `sp` register pointing to the end of the stack.
 
@@ -90,17 +90,16 @@ See [docs/debugging.md](docs/debugging.md) for more info.
 Check out the [documentation](https://riscemu.readthedocs.io/en/latest/riscemu.html).
 
 ## Accessing local documentation:
-To generate your local documentation, first install everything in `sphinx-docs/requirements.txt`. Then run `./generate-docs.sh`, which will 
+To generate your local documentation, first install everything in `sphinx-docs/requirements.txt`. Then run `./generate-docs.sh`, which will
 generate and make all doc files for you. Finally, you can open the docs locall by runnint `open sphinx-docs/build/html/index.html`.
 
 ## Resources:
   * Pseudo ops: https://www.codetd.com/article/8981522
   * detailed instruction definition: https://msyksphinz-self.github.io/riscv-isadoc/html/rvi.html#add
   * RISC-V reference card: https://www.cl.cam.ac.uk/teaching/1617/ECAD+Arch/files/docs/RISCVGreenCardv8-20151013.pdf
-  
+
 ## TODO:
  * Correctly handle 12 and 20 bit immediate (currently not limited to bits at all)
  * Add a cycle limit to the options and CPU to catch infinite loops
  * Move away from `print` and use `logging.logger` instead
  * Writer proper tests
- 
diff --git a/docs/assembly.md b/docs/assembly.md
index 634f774..d68a9a6 100644
--- a/docs/assembly.md
+++ b/docs/assembly.md
@@ -30,8 +30,8 @@ The following pseudo-ops are implemented as of yet:
 * `.global <name>` mark symbol `<name>` as a global symbol. It is available from all loaded programs
 * `.align <bytes>` currently a nop as cpu does not care about alignment as of now
 
-## Sections: 
-Currently only these three sections are supported: 
+## Sections:
+Currently only these three sections are supported:
 * `data` read-write data (non-executable)
 * `rodata` read-only data (non-executable)
 * `text` executable data (read-only)
diff --git a/docs/debugging.md b/docs/debugging.md
index 2bd2ec5..c7ca77d 100644
--- a/docs/debugging.md
+++ b/docs/debugging.md
@@ -37,7 +37,7 @@ uses the `ebreak` instruction to open the debugger. Let's run it and see what ha
 [MMU] Successfully loaded: LoadedExecutable[examples/fibs.asm](base=0x00000100, size=72bytes, sections=data text, run_ptr=0x00000138)
 [CPU] Started running from 0x00000138 (examples/fibs.asm)
 Debug instruction encountered at 0x0000013C
->>> 
+>>>
 ```
 
 In this interactive session, you have access to the cpu, registers, memory and syscall interface. You can look into everything,
@@ -58,8 +58,8 @@ and most common tasks should have helper methods for them.
   * `get(name)` get register content
   * `set(name, val)` set register content
 * `cpu`:
-  * The CPU has the `pc` attribute and `cycle` attribute. Others won't be useful in this context. 
-  
+  * The CPU has the `pc` attribute and `cycle` attribute. Others won't be useful in this context.
+
 **Available helpers are:**
 
 * `dump(regs | addr)` dumps either registers or memory address
@@ -71,4 +71,4 @@ and most common tasks should have helper methods for them.
 
 Example:
 
-![debuggin the fibs program](debug-session.png)
\ No newline at end of file
+![debuggin the fibs program](debug-session.png)
diff --git a/docs/internal-structure.md b/docs/internal-structure.md
index cc0789e..926dad5 100644
--- a/docs/internal-structure.md
+++ b/docs/internal-structure.md
@@ -1,19 +1,19 @@
 # Internal Structure
 
 ## Loading assembly files:
-In order to load an assembly file, you need to instantiate a CPU with the capabilities you want. Loading an assembly 
+In order to load an assembly file, you need to instantiate a CPU with the capabilities you want. Loading an assembly
 file is the done in multiple steps:
 
 
 * An `RiscVInput` is created, this represents the file internally
 * An `RiscVTokenizer` is created by calling `cpu.get_tokenizer()`.
 * The input is tokenized by calling `.tokenize()` on the tokenizer.
-* The tokens can then be converted to an Executable, this will then 
+* The tokens can then be converted to an Executable, this will then
   hold all the information such as name, sections, symbols, etc.
   This is done by creating an `ExecutableParser(tk: RiscVTokenizer)`
   and the calling `parse()`.
 * Now you have a representation of the assembly file that can be loaded
-  into memory by calling `cpu.load(executable)`, this will internally 
+  into memory by calling `cpu.load(executable)`, this will internally
   construct a `LoadedExecutable`, which represents the actual memory
   regions the executable contains (and some meta information such as
   symbols).
@@ -30,4 +30,3 @@ Creating a cpu with certain instruction sets is done by passing the CPU construc
 ```
 cpu = CPU(config, [RV32I, RV32M])
 ```
-
diff --git a/docs/libraries.md b/docs/libraries.md
index 9bfc6f2..a5d4ee3 100644
--- a/docs/libraries.md
+++ b/docs/libraries.md
@@ -13,4 +13,3 @@ You can include the libraries by adding them as arguments (before your main asse
 ```
 
 These libraries are no where near a stable state, so documentation will be scarce. Your best bet would be to `grep` for functionality. Sorry!
-
diff --git a/docs/syscalls.md b/docs/syscalls.md
index aabafc7..834f615 100644
--- a/docs/syscalls.md
+++ b/docs/syscalls.md
@@ -7,7 +7,7 @@ Performing a syscall is quite simple:
     ; set syscall args:
     addi a0, zero, 1    ; exit with code 1
     ; invode syscall handler
-    scall               
+    scall
 ```
 
 The global symbols (e.g. `SCALL_READ`) are loaded by default. If you specify the option `no_syscall_symbols`, they will be omitted.
@@ -47,4 +47,4 @@ Requires flag `--scall-fs` to be set to True
 
 # Extending these syscalls
 
-You can implement your own syscall by adding its code to the `SYSCALLS` dict in the [riscemu/syscalls.py](../riscemu/syscall.py) file, creating a mapping of a syscall code to a name, and then implementing that syscall name in the SyscallInterface class further down that same file. Each syscall method should have the same signature: `read(self, scall: Syscall)`. The `Syscall` object gives you access to the cpu, through which you can access registers and memory. You can look at the `read` or `write` syscalls for further examples. 
+You can implement your own syscall by adding its code to the `SYSCALLS` dict in the [riscemu/syscalls.py](../riscemu/syscall.py) file, creating a mapping of a syscall code to a name, and then implementing that syscall name in the SyscallInterface class further down that same file. Each syscall method should have the same signature: `read(self, scall: Syscall)`. The `Syscall` object gives you access to the cpu, through which you can access registers and memory. You can look at the `read` or `write` syscalls for further examples.
diff --git a/examples/lib/libstring.asm b/examples/lib/libstring.asm
index a95dafe..f2075e3 100644
--- a/examples/lib/libstring.asm
+++ b/examples/lib/libstring.asm
@@ -150,5 +150,3 @@ __memset_loop:
             j    __memset_loop
 __memset_ret:
             ret
-
-
diff --git a/examples/static-data.asm b/examples/static-data.asm
index e521e35..a6b2e54 100644
--- a/examples/static-data.asm
+++ b/examples/static-data.asm
@@ -17,4 +17,4 @@ main:
         print.uhex a0
         // exit
         li  a7, 93
-        ecall
\ No newline at end of file
+        ecall
diff --git a/generate-docs.sh b/generate-docs.sh
index efb35a6..857a983 100755
--- a/generate-docs.sh
+++ b/generate-docs.sh
@@ -35,4 +35,4 @@ cd sphinx-docs
 
 make html
 
-# xdg-open build/html/index.html
\ No newline at end of file
+# xdg-open build/html/index.html
diff --git a/project.toml b/project.toml
index 1870a2e..9787c3b 100644
--- a/project.toml
+++ b/project.toml
@@ -1,4 +1,3 @@
 [build-system]
 requires = ["setuptools", "wheel"]
 build-backend = "setuptools.build_meta"
-
diff --git a/requirements-dev.txt b/requirements-dev.txt
new file mode 100644
index 0000000..d0945fa
--- /dev/null
+++ b/requirements-dev.txt
@@ -0,0 +1,3 @@
+black==23.3.0
+pre-commit==3.2.2
+pytest==7.3.1
\ No newline at end of file
diff --git a/riscemu/priv/Exceptions.py b/riscemu/priv/Exceptions.py
index f9569b4..3b039cd 100644
--- a/riscemu/priv/Exceptions.py
+++ b/riscemu/priv/Exceptions.py
@@ -42,7 +42,7 @@ class CpuTrap(BaseException):
 
     priv: PrivModes
     """
-    The privilege level this trap targets 
+    The privilege level this trap targets
     """
 
     def __init__(
diff --git a/riscemu/syscall.py b/riscemu/syscall.py
index 9401c5f..d9d2a7b 100644
--- a/riscemu/syscall.py
+++ b/riscemu/syscall.py
@@ -22,7 +22,7 @@ SYSCALLS = {
 """
 This dict contains a mapping for all available syscalls (code->name)
 
-If you wish to add a syscall to the built-in system, you can extend this 
+If you wish to add a syscall to the built-in system, you can extend this
 dictionary and implement a method with the same name on the SyscallInterface
 class.
 """
diff --git a/riscemu/types/instruction_context.py b/riscemu/types/instruction_context.py
index db50cec..ab5ebde 100644
--- a/riscemu/types/instruction_context.py
+++ b/riscemu/types/instruction_context.py
@@ -18,8 +18,8 @@ class InstructionContext:
 
     numbered_labels: Dict[str, List[T_RelativeAddress]]
     """
-    This dictionary maps numbered labels (which can occur multiple times) to a list of (block-relative) addresses where 
-    the label was placed 
+    This dictionary maps numbered labels (which can occur multiple times) to a list of (block-relative) addresses where
+    the label was placed
     """
 
     global_symbol_dict: Dict[str, T_AbsoluteAddress]
diff --git a/sphinx-docs/.gitignore b/sphinx-docs/.gitignore
index ab8b79e..49123cb 100644
--- a/sphinx-docs/.gitignore
+++ b/sphinx-docs/.gitignore
@@ -1,4 +1,4 @@
 build
 source/riscemu*.rst
 source/modules.rst
-source/help
\ No newline at end of file
+source/help
diff --git a/sphinx-docs/source/index.rst b/sphinx-docs/source/index.rst
index fea3c32..0051397 100644
--- a/sphinx-docs/source/index.rst
+++ b/sphinx-docs/source/index.rst
@@ -59,4 +59,4 @@ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
 AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-SOFTWARE.
\ No newline at end of file
+SOFTWARE.