anton/riscemu
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

minor instruction fixes such as added assertions

Browse Source
This commit is contained in:
Anton Lydike 2021-04-17 23:14:56 +02:00
parent 5bdd866472
commit 99de083894
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
riscemu/CPU.py
View File

@ -102,7 +102,7 @@ class CPU:
reg = ins.get_reg(1)
imm = ins.get_imm(2)
addr = self.regs.get(reg) + imm
self.mmu.write(addr, 4, int_to_bytes(self.regs.get(reg), 4))
self.mmu.write(addr, 4, int_to_bytes(self.regs.get(src), 4))
def instruction_sll(self, ins: 'LoadedInstruction'):
INS_NOT_IMPLEMENTED(ins)
@ -123,6 +123,7 @@ class CPU:
INS_NOT_IMPLEMENTED(ins)
def instruction_add(self, ins: 'LoadedInstruction'):
ASSERT_LEN(ins.args, 3)
dst = ins.get_reg(0)
src1 = ins.get_reg(1)
src2 = ins.get_reg(2)
@ -142,7 +143,6 @@ class CPU:
)
def instruction_sub(self, ins: 'LoadedInstruction'):
INS_NOT_IMPLEMENTED(ins)
def instruction_lui(self, ins: 'LoadedInstruction'):