diff --git a/riscemu/MMU.py b/riscemu/MMU.py
index e2e0ccb..1a94fca 100644
--- a/riscemu/MMU.py
+++ b/riscemu/MMU.py
@@ -62,4 +62,6 @@ class MMU:
         sec = self.get_sec_containing(addr)
         return sec.write(addr - sec.base, size, data)
 
-
+    # debugging interactions:
+    def dump(self, addr, *args, **kwargs):
+        self.get_sec_containing(addr).dump(addr, *args, **kwargs)
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