diff --git a/riscemu/MMU.py b/riscemu/MMU.py
index 2f6a167..e9be0d1 100644
--- a/riscemu/MMU.py
+++ b/riscemu/MMU.py
@@ -53,10 +53,11 @@ class MMU:
 
         return loaded_bin
 
-    def get_sec_containing(self, addr: int):
+    def get_sec_containing(self, addr: int) -> Optional[LoadedMemorySection]:
         for sec in self.sections:
             if sec.base <= addr < sec.base + sec.size:
                 return sec
+        return None
 
     def read_ins(self, addr: int):
         sec = self.get_sec_containing(addr)
@@ -72,7 +73,10 @@ class MMU:
 
     # debugging interactions:
     def dump(self, addr, *args, **kwargs):
-        self.get_sec_containing(addr).dump(addr, *args, **kwargs)
+        sec = self.get_sec_containing(addr)
+        if sec is None:
+            return
+        sec.dump(addr, *args, **kwargs)
 
     def symbol(self, symb:str):
         print(FMT_MEM + "Lookup for symbol {}:".format(symb) + FMT_NONE)
diff --git a/riscemu/debug.py b/riscemu/debug.py
index 0b79957..c739791 100644
--- a/riscemu/debug.py
+++ b/riscemu/debug.py
@@ -17,9 +17,15 @@ def launch_debug_session(cpu: 'CPU', mmu: 'MMU', reg: 'Registers', prompt=""):
     mem = mmu
     syscall_interface = cpu.syscall_int
 
-    vars = globals()
-    vars.update(locals())
+    def dump(what, *args, **kwargs):
+        if isinstance(what, Registers):
+            regs.dump(*args, **kwargs)
+        else:
+            mmu.dump(what, *args, **kwargs)
 
-    readline.set_completer(rlcompleter.Completer(vars).complete)
+    sess_vars = globals()
+    sess_vars.update(locals())
+
+    readline.set_completer(rlcompleter.Completer(sess_vars).complete)
     readline.parse_and_bind("tab: complete")
-    code.InteractiveConsole(vars).interact(banner=prompt, exitmsg="Resuming simulation")
+    code.InteractiveConsole(sess_vars).interact(banner=prompt, exitmsg="Resuming simulation")