From 4159d1609b528c8672cd6531a1e9e5061106cd22 Mon Sep 17 00:00:00 2001
From: Anton Lydike <me@antonlydike.de>
Date: Sat, 17 Apr 2021 20:24:38 +0200
Subject: [PATCH] added run config

---
 riscemu/CPU.py        | 29 +++++++++++++----------------
 riscemu/Config.py     |  8 ++++++++
 riscemu/Executable.py |  2 +-
 riscemu/MMU.py        | 10 +++++++---
 riscemu/Registers.py  |  0
 riscemu/__init__.py   |  4 +++-
 riscemu/helpers.py    |  5 +++++
 riscemu/main.py       |  0
 8 files changed, 37 insertions(+), 21 deletions(-)
 create mode 100644 riscemu/Config.py
 create mode 100644 riscemu/Registers.py
 create mode 100644 riscemu/main.py

diff --git a/riscemu/CPU.py b/riscemu/CPU.py
index 3044e31..254d658 100644
--- a/riscemu/CPU.py
+++ b/riscemu/CPU.py
@@ -4,25 +4,20 @@ from collections import defaultdict
 
 from .Exceptions import *
 from .helpers import *
+from .Config import RunConfig
 
 import typing
+
 if typing.TYPE_CHECKING:
     from . import MMU, Executable, LoadedExecutable, LoadedInstruction
 
-COLOR = True
-
-FMT_ORANGE = '\033[33m'
-FMT_GRAY = '\033[37m'
-FMT_BOLD = '\033[1m'
-FMT_NONE = '\033[0m'
-FMT_UNDERLINE = '\033[4m'
-
 
 class Registers:
-    def __init__(self):
+    def __init__(self, conf: RunConfig):
         self.vals = defaultdict(lambda: 0)
         self.last_mod = None
         self.last_access = None
+        self.conf = conf
 
     def dump(self, small=False):
         named_regs = [self.reg_repr(reg) for reg in Registers.named_registers()]
@@ -67,6 +62,8 @@ class Registers:
 
     def reg_repr(self, reg):
         txt = '{:4}=0x{:08X}'.format(reg, self.get(reg))
+        if not self.conf.color:
+            return txt
         if reg == 'fp':
             reg = 's0'
         if reg == self.last_mod:
@@ -112,14 +109,16 @@ class Registers:
     def named_registers():
         return ['zero', 'ra', 'sp', 'gp', 'tp', 'fp']
 
+
 class CPU:
-    def __init__(self):
+    def __init__(self, conf: RunConfig):
         from . import MMU, Executable, LoadedExecutable, LoadedInstruction
 
-        self.mmu = MMU()
+        self.mmu = MMU(conf)
         self.regs = Registers()
         self.pc = 0
         self.exit = False
+        self.conf = conf
 
         self.syscall_int = SyscallInterface()
 
@@ -289,7 +288,6 @@ class CPU:
         if self.regs.get(reg1) < self.regs.get(reg2):
             self.pc = dest
 
-
     def instruction_bge(self, ins: 'LoadedInstruction'):
         INS_NOT_IMPLEMENTED(ins)
 
@@ -325,8 +323,9 @@ class CPU:
         INS_NOT_IMPLEMENTED(ins)
 
     def instruction_dbg(self, ins: 'LoadedInstruction'):
-        import code
-        code.interact(local=dict(globals(), **locals()))
+        if self.conf.debug_instruction:
+            import code
+            code.interact(local=dict(globals(), **locals()))
 
     @staticmethod
     def all_instructions():
@@ -345,5 +344,3 @@ class SyscallInterface:
     def handle_syscall(self, scall: Syscall):
         print("syscall {} received!".format(scall.id))
         scall.registers.dump_reg_a()
-
-
diff --git a/riscemu/Config.py b/riscemu/Config.py
new file mode 100644
index 0000000..676728a
--- /dev/null
+++ b/riscemu/Config.py
@@ -0,0 +1,8 @@
+from dataclasses import dataclass
+
+@dataclass()
+class RunConfig:
+    color = True
+    preffered_stack_size = None
+    debug_instruction = True
+
diff --git a/riscemu/Executable.py b/riscemu/Executable.py
index 62992a6..ef02f38 100644
--- a/riscemu/Executable.py
+++ b/riscemu/Executable.py
@@ -53,7 +53,7 @@ class InstructionMemorySection(MemorySection):
         ]
 
 
-@dataclass(frozen=True)
+@dataclass()
 class Executable:
     run_ptr: Tuple[str, int]
     sections: Dict[str, MemorySection]
diff --git a/riscemu/MMU.py b/riscemu/MMU.py
index 3a83c27..e2e0ccb 100644
--- a/riscemu/MMU.py
+++ b/riscemu/MMU.py
@@ -1,5 +1,4 @@
-from dataclasses import dataclass
-
+from .Config import RunConfig
 from .Executable import Executable, LoadedExecutable, LoadedMemorySection
 from .helpers import align_addr
 from .Exceptions import OutOfMemoryEsception
@@ -14,10 +13,11 @@ class MMU:
     binaries: List[LoadedExecutable]
     last_bin: Optional[LoadedExecutable] = None
 
-    def __init__(self):
+    def __init__(self, conf: RunConfig):
         self.sections = list()
         self.binaries = list()
         self.last_bin = None
+        self.conf = conf
 
     def load_bin(self, bin: Executable):
         if self.last_bin is None:
@@ -27,6 +27,10 @@ class MMU:
         # align to 8 byte word
         addr = align_addr(addr)
 
+        # apply preferred stack size from config
+        if bin.stack_pref is None:
+            bin.stack_pref = self.conf.preffered_stack_size
+
         loaded_bin = LoadedExecutable(bin, addr)
 
         if loaded_bin.size + addr > self.max_size:
diff --git a/riscemu/Registers.py b/riscemu/Registers.py
new file mode 100644
index 0000000..e69de29
diff --git a/riscemu/__init__.py b/riscemu/__init__.py
index 7277732..e31ff0c 100644
--- a/riscemu/__init__.py
+++ b/riscemu/__init__.py
@@ -10,4 +10,6 @@ from .ExecutableParser import ExecutableParser
 
 from .MMU import MMU
 
-from .CPU import CPU, Registers, Syscall, SyscallInterface
\ No newline at end of file
+from .CPU import CPU, Registers, Syscall, SyscallInterface
+
+from .Config import RunConfig
\ No newline at end of file
diff --git a/riscemu/helpers.py b/riscemu/helpers.py
index 2765d1c..ac8b31c 100644
--- a/riscemu/helpers.py
+++ b/riscemu/helpers.py
@@ -36,3 +36,8 @@ def int_from_bytes(bytes):
         return num - 2 ** (8 * len(bytes))
     return num
 
+FMT_ORANGE = '\033[33m'
+FMT_GRAY = '\033[37m'
+FMT_BOLD = '\033[1m'
+FMT_NONE = '\033[0m'
+FMT_UNDERLINE = '\033[4m'
\ No newline at end of file
diff --git a/riscemu/main.py b/riscemu/main.py
new file mode 100644
index 0000000..e69de29