From 3d07c97a5283160ac71876b717e5489f86599e01 Mon Sep 17 00:00:00 2001 From: Anton Lydike Date: Tue, 8 Jun 2021 16:33:48 +0200 Subject: [PATCH] [PrivCPU] improved step function performance by checking time every tenth cycle --- riscemu/priv/PrivCPU.py | 26 ++++++++++++++++---------- 1 file changed, 16 insertions(+), 10 deletions(-) diff --git a/riscemu/priv/PrivCPU.py b/riscemu/priv/PrivCPU.py index 6d0e53a..12089d6 100644 --- a/riscemu/priv/PrivCPU.py +++ b/riscemu/priv/PrivCPU.py @@ -160,10 +160,9 @@ class PrivCPU(CPU): def step(self, verbose=True): try: - if self.cycle % 1000 == 0: - self._perf_counters.append((time.perf_counter_ns(), self.cycle)) self.cycle += 1 - self._timer_step() + if self.cycle % 10 == 0: + self._timer_step() self._check_interrupt() ins = self.mmu.read_ins(self.pc) if verbose: @@ -207,6 +206,9 @@ class PrivCPU(CPU): self.pc = mtvec if mtvec & 0b11 == 1: self.pc = (mtvec & 0b11111111111111111111111111111100) + (trap.code * 4) + self.record_perf_profile() + if len(self._perf_counters) % 100 == 0: + self.show_perf() def show_perf(self): timed = 0 @@ -214,19 +216,23 @@ class PrivCPU(CPU): cps_list = list() print(FMT_CPU + "[CPU] Performance overview:") - for time_ns, cycle in self._perf_counters[-11:]: + for time_ns, cycle in self._perf_counters: if cycled == 0: cycled = cycle timed = time_ns continue cps = (cycle - cycled) / (time_ns - timed) * 1000000000 - print(" {:03d} cycles in {:08d}ns ({:.2f} cycles/s)".format( - cycle - cycled, - time_ns - timed, - cps - )) + #print(" {:03d} cycles in {:08d}ns ({:.2f} cycles/s)".format( + # cycle - cycled, + # time_ns - timed, + # cps + #)) cycled = cycle timed = time_ns cps_list.append(cps) - print(" on average {:.0f} cycles/s".format(sum(cps_list) / len(cps_list)) + FMT_NONE) \ No newline at end of file + print(" on average {:.0f} cycles/s".format(sum(cps_list) / len(cps_list)) + FMT_NONE) + self._perf_counters = list() + + def record_perf_profile(self): + self._perf_counters.append((time.perf_counter_ns(), self.cycle)) \ No newline at end of file