refactored instruction sets to be modular
Anton Lydike
4 years ago
parent
c20ab4cfb1
commit
3ce42079d4
@ -1,29 +0,0 @@
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.stack 0xFFFF
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.data 0x200
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fibs: .space 56
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.text
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main:
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func_fibs:
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addi s1, zero, 0 # storage index
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addi s2, zero, 56 # last storage index
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addi t0, zero, 1 # t0 = F_{i}
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addi t1, zero, 1 # t1 = F_{i+1}
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loop:
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sw t0, fibs(s1) # save
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add t2, t1, t0 # t2 = F_{i+2}
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addi t0, t1, 0 # t0 = t1
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addi t1, t2, 0 # t1 = t2
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addi s1, s1, 4 # increment storage pointer
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blt s1, s2, loop # loop as long as we did not reach array length
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# exit gracefully
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addi a0, zero, 0
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addi a7, zero, 93
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ebreak # launch debugger
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scall # exit with code 0
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.set test_val, 0xFF
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.global func_fibs
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@ -0,0 +1,46 @@
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import typing
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from abc import ABC, abstractmethod
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from ..CPU import *
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class InstructionSet(ABC):
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"""
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Represents a collection of instructions
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"""
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def __init__(self, name):
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self.name = name
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self.cpu: typing.Optional['CPU'] = None
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self.mmu: typing.Optional['MMU'] = None
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self.regs: typing.Optional['Registers'] = None
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def load(self, cpu: 'CPU'):
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self.cpu = cpu
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self.mmu = cpu.mmu
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self.regs = cpu.regs
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return {
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name: ins for name, ins in self.get_instructions()
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}
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def get_instructions(self):
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for member in dir(self):
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if member.startswith('instruction_'):
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yield member[12:].replace('_', '.'), getattr(self, member)
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def parse_mem_ins(self, ins: 'LoadedInstruction'):
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return self.cpu.parse_mem_ins(ins)
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@property
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def pc(self):
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return self.cpu.pc
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@pc.setter
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def pc(self, val):
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self.cpu.pc = val
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def __repr__(self):
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return "InstructionSet[{}] with {} instructions".format(
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self.name,
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len(list(self.get_instructions()))
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)
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@ -0,0 +1,293 @@
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from .InstructionSet import *
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from ..helpers import int_from_bytes, int_to_bytes, to_unsigned, to_signed
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class RV32I(InstructionSet):
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def __init__(self):
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super().__init__('RV32I')
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def instruction_lb(self, ins: 'LoadedInstruction'):
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rd, addr = self.parse_mem_ins(ins)
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self.regs.set(rd, int_from_bytes(self.mmu.read(addr, 1)))
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def instruction_lh(self, ins: 'LoadedInstruction'):
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rd, addr = self.parse_mem_ins(ins)
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self.regs.set(rd, int_from_bytes(self.mmu.read(addr, 2)))
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def instruction_lw(self, ins: 'LoadedInstruction'):
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rd, addr = self.parse_mem_ins(ins)
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self.regs.set(rd, int_from_bytes(self.mmu.read(addr, 4)))
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def instruction_lbu(self, ins: 'LoadedInstruction'):
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rd, addr = self.parse_mem_ins(ins)
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self.regs.set(rd, int_from_bytes(self.mmu.read(addr, 1), unsigned=True))
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def instruction_lhu(self, ins: 'LoadedInstruction'):
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rd, addr = self.parse_mem_ins(ins)
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self.regs.set(rd, int_from_bytes(self.mmu.read(addr, 2), unsigned=True))
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def instruction_sb(self, ins: 'LoadedInstruction'):
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rd, addr = self.parse_mem_ins(ins)
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self.mmu.write(addr, 1, int_to_bytes(self.regs.get(rd), 1))
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def instruction_sh(self, ins: 'LoadedInstruction'):
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rd, addr = self.parse_mem_ins(ins)
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self.mmu.write(addr, 2, int_to_bytes(self.regs.get(rd), 2))
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def instruction_sw(self, ins: 'LoadedInstruction'):
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rd, addr = self.parse_mem_ins(ins)
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self.mmu.write(addr, 4, int_to_bytes(self.regs.get(rd), 4))
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def instruction_sll(self, ins: 'LoadedInstruction'):
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ASSERT_LEN(ins.args, 3)
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dst = ins.get_reg(0)
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src1 = ins.get_reg(1)
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src2 = ins.get_reg(2)
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self.regs.set(
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dst,
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to_signed(to_unsigned(self.regs.get(src1)) << (self.regs.get(src2) & 0b11111))
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)
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def instruction_slli(self, ins: 'LoadedInstruction'):
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ASSERT_LEN(ins.args, 3)
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dst = ins.get_reg(0)
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src1 = ins.get_reg(1)
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imm = ins.get_imm(2)
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self.regs.set(
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dst,
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to_signed(to_unsigned(self.regs.get(src1)) << (imm & 0b11111))
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)
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def instruction_srl(self, ins: 'LoadedInstruction'):
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ASSERT_LEN(ins.args, 3)
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dst = ins.get_reg(0)
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src1 = ins.get_reg(1)
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src2 = ins.get_reg(2)
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self.regs.set(
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dst,
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to_signed(to_unsigned(self.regs.get(src1)) >> (self.regs.get(src2) & 0b11111))
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)
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def instruction_srli(self, ins: 'LoadedInstruction'):
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ASSERT_LEN(ins.args, 3)
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dst = ins.get_reg(0)
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src1 = ins.get_reg(1)
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imm = ins.get_imm(2)
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self.regs.set(
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dst,
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to_signed(to_unsigned(self.regs.get(src1)) >> (imm & 0b11111))
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)
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def instruction_sra(self, ins: 'LoadedInstruction'):
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ASSERT_LEN(ins.args, 3)
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dst = ins.get_reg(0)
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src1 = ins.get_reg(1)
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src2 = ins.get_reg(2)
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self.regs.set(
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dst,
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self.regs.get(src1) >> (self.regs.get(src2) & 0b11111)
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)
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def instruction_srai(self, ins: 'LoadedInstruction'):
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ASSERT_LEN(ins.args, 3)
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dst = ins.get_reg(0)
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src1 = ins.get_reg(1)
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imm = ins.get_imm(2)
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self.regs.set(
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dst,
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self.regs.get(src1) >> (imm & 0b11111)
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)
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def instruction_add(self, ins: 'LoadedInstruction'):
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ASSERT_LEN(ins.args, 3)
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dst = ins.get_reg(0)
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src1 = ins.get_reg(1)
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src2 = ins.get_reg(2)
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self.regs.set(
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dst,
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self.regs.get(src1) + self.regs.get(src2)
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)
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def instruction_addi(self, ins: 'LoadedInstruction'):
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ASSERT_LEN(ins.args, 3)
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dst = ins.get_reg(0)
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src1 = ins.get_reg(1)
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imm = ins.get_imm(2)
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self.regs.set(
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dst,
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self.regs.get(src1) + imm
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)
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def instruction_sub(self, ins: 'LoadedInstruction'):
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ASSERT_LEN(ins.args, 3)
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dst = ins.get_reg(0)
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src1 = ins.get_reg(1)
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src2 = ins.get_reg(2)
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self.regs.set(
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dst,
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self.regs.get(src1) - self.regs.get(src2)
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)
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def instruction_lui(self, ins: 'LoadedInstruction'):
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INS_NOT_IMPLEMENTED(ins)
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def instruction_auipc(self, ins: 'LoadedInstruction'):
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INS_NOT_IMPLEMENTED(ins)
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def instruction_xor(self, ins: 'LoadedInstruction'):
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ASSERT_LEN(ins.args, 3)
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dst = ins.get_reg(0)
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src1 = ins.get_reg(1)
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src2 = ins.get_reg(2)
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self.regs.set(
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dst,
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self.regs.get(src1) ^ self.regs.get(src2)
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)
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def instruction_xori(self, ins: 'LoadedInstruction'):
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INS_NOT_IMPLEMENTED(ins)
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def instruction_or(self, ins: 'LoadedInstruction'):
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ASSERT_LEN(ins.args, 3)
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dst = ins.get_reg(0)
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src1 = ins.get_reg(1)
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src2 = ins.get_reg(2)
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self.regs.set(
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dst,
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self.regs.get(src1) | self.regs.get(src2)
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)
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def instruction_ori(self, ins: 'LoadedInstruction'):
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INS_NOT_IMPLEMENTED(ins)
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def instruction_and(self, ins: 'LoadedInstruction'):
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ASSERT_LEN(ins.args, 3)
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dst = ins.get_reg(0)
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src1 = ins.get_reg(1)
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src2 = ins.get_reg(2)
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self.regs.set(
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dst,
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self.regs.get(src1) & self.regs.get(src2)
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)
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def instruction_andi(self, ins: 'LoadedInstruction'):
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INS_NOT_IMPLEMENTED(ins)
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def instruction_slt(self, ins: 'LoadedInstruction'):
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ASSERT_LEN(ins.args, 3)
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dst = ins.get_reg(0)
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src1 = ins.get_reg(1)
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src2 = ins.get_reg(2)
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self.regs.set(
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dst,
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int(self.regs.get(src1) < self.regs.get(src2))
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)
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def instruction_slti(self, ins: 'LoadedInstruction'):
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INS_NOT_IMPLEMENTED(ins)
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def instruction_sltu(self, ins: 'LoadedInstruction'):
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ASSERT_LEN(ins.args, 3)
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dst = ins.get_reg(0)
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src1 = ins.get_reg(1)
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src2 = ins.get_reg(2)
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self.regs.set(
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dst,
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int(to_unsigned(self.regs.get(src1)) < to_unsigned(self.regs.get(src2)))
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)
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def instruction_sltiu(self, ins: 'LoadedInstruction'):
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INS_NOT_IMPLEMENTED(ins)
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def instruction_beq(self, ins: 'LoadedInstruction'):
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ASSERT_LEN(ins.args, 3)
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reg1 = ins.get_reg(0)
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reg2 = ins.get_reg(1)
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dest = ins.get_imm(2)
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if self.regs.get(reg1) == self.regs.get(reg2):
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self.pc = dest
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def instruction_bne(self, ins: 'LoadedInstruction'):
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ASSERT_LEN(ins.args, 3)
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reg1 = ins.get_reg(0)
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reg2 = ins.get_reg(1)
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dest = ins.get_imm(2)
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if self.regs.get(reg1) != self.regs.get(reg2):
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self.pc = dest
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def instruction_blt(self, ins: 'LoadedInstruction'):
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ASSERT_LEN(ins.args, 3)
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reg1 = ins.get_reg(0)
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reg2 = ins.get_reg(1)
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dest = ins.get_imm(2)
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if self.regs.get(reg1) < self.regs.get(reg2):
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self.pc = dest
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def instruction_bge(self, ins: 'LoadedInstruction'):
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ASSERT_LEN(ins.args, 3)
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reg1 = ins.get_reg(0)
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reg2 = ins.get_reg(1)
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dest = ins.get_imm(2)
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if self.regs.get(reg1) >= self.regs.get(reg2):
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self.pc = dest
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def instruction_bltu(self, ins: 'LoadedInstruction'):
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ASSERT_LEN(ins.args, 3)
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reg1 = to_unsigned(ins.get_reg(0))
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reg2 = to_unsigned(ins.get_reg(1))
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dest = ins.get_imm(2)
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if self.regs.get(reg1) < self.regs.get(reg2):
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self.pc = dest
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def instruction_bgeu(self, ins: 'LoadedInstruction'):
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ASSERT_LEN(ins.args, 3)
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reg1 = to_unsigned(ins.get_reg(0))
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reg2 = to_unsigned(ins.get_reg(1))
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dest = ins.get_imm(2)
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if self.regs.get(reg1) >= self.regs.get(reg2):
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self.pc = dest
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# technically deprecated
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def instruction_j(self, ins: 'LoadedInstruction'):
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ASSERT_LEN(ins.args, 1)
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addr = ins.get_imm(0)
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self.pc = addr
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def instruction_jal(self, ins: 'LoadedInstruction'):
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reg = 'ra' # default register is ra
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if len(ins.args) == 1:
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addr = ins.get_imm(0)
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else:
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ASSERT_LEN(ins.args, 2)
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reg = ins.get_reg(0)
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addr = ins.get_imm(1)
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self.regs.set(reg, self.pc)
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self.pc = addr
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def instruction_jalr(self, ins: 'LoadedInstruction'):
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ASSERT_LEN(ins.args, 2)
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reg = ins.get_reg(0)
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addr = ins.get_imm(1)
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self.regs.set(reg, self.pc)
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self.pc = addr
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def instruction_ret(self, ins: 'LoadedInstruction'):
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ASSERT_LEN(ins.args, 0)
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self.pc = self.regs.get('ra')
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def instruction_ecall(self, ins: 'LoadedInstruction'):
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self.instruction_scall(ins)
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def instruction_ebreak(self, ins: 'LoadedInstruction'):
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self.instruction_sbreak(ins)
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def instruction_scall(self, ins: 'LoadedInstruction'):
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ASSERT_LEN(ins.args, 0)
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syscall = Syscall(self.regs.get('a7'), self.regs, self.cpu)
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self.cpu.syscall_int.handle_syscall(syscall)
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def instruction_sbreak(self, ins: 'LoadedInstruction'):
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launch_debug_session(self.cpu, self.mmu, self.regs, "Debug instruction encountered at 0x{:08X}".format(self.pc))
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def instruction_nop(self, ins: 'LoadedInstruction'):
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pass
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