refactored instruction sets to be modular
This commit is contained in:
Anton Lydike
parent
c20ab4cfb1
commit
3ce42079d4
29
fibs.asm
29
fibs.asm
@ -1,29 +0,0 @@
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.stack 0xFFFF
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.data 0x200
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fibs: .space 56
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.text
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main:
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func_fibs:
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addi s1, zero, 0 # storage index
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addi s2, zero, 56 # last storage index
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addi t0, zero, 1 # t0 = F_{i}
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addi t1, zero, 1 # t1 = F_{i+1}
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loop:
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sw t0, fibs(s1) # save
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add t2, t1, t0 # t2 = F_{i+2}
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addi t0, t1, 0 # t0 = t1
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addi t1, t2, 0 # t1 = t2
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addi s1, s1, 4 # increment storage pointer
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blt s1, s2, loop # loop as long as we did not reach array length
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# exit gracefully
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addi a0, zero, 0
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addi a7, zero, 93
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ebreak # launch debugger
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scall # exit with code 0
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.set test_val, 0xFF
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.global func_fibs
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341
riscemu/CPU.py
341
riscemu/CPU.py
@ -1,40 +1,62 @@
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import traceback
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from typing import Tuple
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from typing import Tuple, List, Dict, Callable
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from .Tokenizer import RiscVTokenizer
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from .Syscall import *
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from .Exceptions import *
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from .helpers import *
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from .MMU import MMU
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from .Config import RunConfig
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from .Registers import Registers
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from .Syscall import SyscallInterface, Syscall
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from .debug import launch_debug_session
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import typing
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if typing.TYPE_CHECKING:
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from . import MMU, Executable, LoadedExecutable, LoadedInstruction
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from . import Executable, LoadedExecutable, LoadedInstruction
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from .Instructions.InstructionSet import InstructionSet
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class CPU:
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def __init__(self, conf: RunConfig):
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from . import MMU
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def __init__(self, conf: RunConfig, instruction_sets: List['InstructionSet']):
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# setup CPU states
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self.pc = 0
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self.cycle = 0
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self.exit = False
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self.exit_code = 0
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self.conf = conf
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# setup MMU, registers and syscall handlers
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self.mmu = MMU(conf)
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self.regs = Registers(conf)
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self.syscall_int = SyscallInterface()
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# load all instruction sets
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self.sets = instruction_sets
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self.instructions: Dict[str, Callable[[LoadedInstruction], None]] = dict()
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for ins_set in instruction_sets:
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self.instructions.update(ins_set.load(self))
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# provide global syscall symbols if option is set
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if conf.include_scall_symbols:
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self.mmu.global_symbols.update(self.syscall_int.get_syscall_symbols())
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def get_tokenizer(self, input):
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"""
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Returns a tokenizer that respects the language of the CPU
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"""
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return RiscVTokenizer(input, self.all_instructions())
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def load(self, e: 'Executable'):
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"""
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Load an executable into Memory
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"""
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return self.mmu.load_bin(e)
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def run_loaded(self, le: 'LoadedExecutable'):
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"""
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Run a loaded executable
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"""
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self.pc = le.run_ptr
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sp, hp = le.stack_heap
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self.regs.set('sp', sp)
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@ -55,7 +77,6 @@ class CPU:
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except RiscemuBaseException as ex:
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print(FMT_ERROR + "[CPU] excpetion caught at 0x{:08X}: {}:".format(self.pc-1, ins) + FMT_NONE)
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print(" " + ex.message())
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#traceback.print_exception(type(ex), ex, ex.__traceback__)
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if self.conf.debug_on_exception:
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launch_debug_session(self, self.mmu, self.regs,
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"Exception encountered, launching debug:".format(self.pc-1))
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@ -63,14 +84,13 @@ class CPU:
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print(FMT_CPU + "Program exited with code {}".format(self.exit_code) + FMT_NONE)
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def __run_instruction(self, ins: 'LoadedInstruction'):
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name = '_CPU__instruction_' + ins.name
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if hasattr(self, name):
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getattr(self, name)(ins)
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if ins.name in self.instructions:
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self.instructions[ins.name](ins)
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else:
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# this should never be reached, as unknown instructions are imparsable
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# this should never be reached, as unknown instructions are imparseable
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raise RuntimeError("Unknown instruction: {}".format(ins))
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def __parse_mem_ins(self, ins: 'LoadedInstruction') -> Tuple[str, int]:
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def parse_mem_ins(self, ins: 'LoadedInstruction') -> Tuple[str, int]:
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"""
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parses both rd, rs1, imm and rd, imm(rs1) arguments and returns (rd, imm+rs1)
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(so a register and address tuple for memory instructions)
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@ -87,299 +107,12 @@ class CPU:
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rd = ins.get_reg(0)
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return rd, self.regs.get(rs1) + imm
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def __instruction_lb(self, ins: 'LoadedInstruction'):
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rd, addr = self.__parse_mem_ins(ins)
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self.regs.set(rd, int_from_bytes(self.mmu.read(addr, 1)))
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def __instruction_lh(self, ins: 'LoadedInstruction'):
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rd, addr = self.__parse_mem_ins(ins)
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self.regs.set(rd, int_from_bytes(self.mmu.read(addr, 2)))
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def __instruction_lw(self, ins: 'LoadedInstruction'):
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rd, addr = self.__parse_mem_ins(ins)
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self.regs.set(rd, int_from_bytes(self.mmu.read(addr, 4)))
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def __instruction_lbu(self, ins: 'LoadedInstruction'):
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rd, addr = self.__parse_mem_ins(ins)
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self.regs.set(rd, int_from_bytes(self.mmu.read(addr, 1), unsigned=True))
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def __instruction_lhu(self, ins: 'LoadedInstruction'):
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rd, addr = self.__parse_mem_ins(ins)
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self.regs.set(rd, int_from_bytes(self.mmu.read(addr, 2), unsigned=True))
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def __instruction_sb(self, ins: 'LoadedInstruction'):
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rd, addr = self.__parse_mem_ins(ins)
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self.mmu.write(addr, 1, int_to_bytes(self.regs.get(rd), 1))
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def __instruction_sh(self, ins: 'LoadedInstruction'):
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rd, addr = self.__parse_mem_ins(ins)
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self.mmu.write(addr, 2, int_to_bytes(self.regs.get(rd), 2))
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def __instruction_sw(self, ins: 'LoadedInstruction'):
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rd, addr = self.__parse_mem_ins(ins)
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self.mmu.write(addr, 4, int_to_bytes(self.regs.get(rd), 4))
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def __instruction_sll(self, ins: 'LoadedInstruction'):
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ASSERT_LEN(ins.args, 3)
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dst = ins.get_reg(0)
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src1 = ins.get_reg(1)
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src2 = ins.get_reg(2)
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self.regs.set(
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dst,
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to_signed(to_unsigned(self.regs.get(src1)) << (self.regs.get(src2) & 0b11111))
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)
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def __instruction_slli(self, ins: 'LoadedInstruction'):
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ASSERT_LEN(ins.args, 3)
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dst = ins.get_reg(0)
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src1 = ins.get_reg(1)
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imm = ins.get_imm(2)
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self.regs.set(
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dst,
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to_signed(to_unsigned(self.regs.get(src1)) << (imm & 0b11111))
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)
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def __instruction_srl(self, ins: 'LoadedInstruction'):
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ASSERT_LEN(ins.args, 3)
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dst = ins.get_reg(0)
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src1 = ins.get_reg(1)
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src2 = ins.get_reg(2)
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self.regs.set(
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dst,
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to_signed(to_unsigned(self.regs.get(src1)) >> (self.regs.get(src2) & 0b11111))
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)
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def __instruction_srli(self, ins: 'LoadedInstruction'):
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ASSERT_LEN(ins.args, 3)
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dst = ins.get_reg(0)
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src1 = ins.get_reg(1)
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imm = ins.get_imm(2)
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self.regs.set(
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dst,
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to_signed(to_unsigned(self.regs.get(src1)) >> (imm & 0b11111))
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)
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def __instruction_sra(self, ins: 'LoadedInstruction'):
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ASSERT_LEN(ins.args, 3)
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dst = ins.get_reg(0)
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src1 = ins.get_reg(1)
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src2 = ins.get_reg(2)
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self.regs.set(
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dst,
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self.regs.get(src1) >> (self.regs.get(src2) & 0b11111)
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)
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def __instruction_srai(self, ins: 'LoadedInstruction'):
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ASSERT_LEN(ins.args, 3)
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dst = ins.get_reg(0)
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src1 = ins.get_reg(1)
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imm = ins.get_imm(2)
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self.regs.set(
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dst,
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self.regs.get(src1) >> (imm & 0b11111)
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)
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def __instruction_add(self, ins: 'LoadedInstruction'):
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ASSERT_LEN(ins.args, 3)
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dst = ins.get_reg(0)
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src1 = ins.get_reg(1)
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src2 = ins.get_reg(2)
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self.regs.set(
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dst,
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self.regs.get(src1) + self.regs.get(src2)
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)
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def __instruction_addi(self, ins: 'LoadedInstruction'):
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ASSERT_LEN(ins.args, 3)
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dst = ins.get_reg(0)
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src1 = ins.get_reg(1)
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imm = ins.get_imm(2)
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self.regs.set(
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dst,
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self.regs.get(src1) + imm
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)
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def __instruction_sub(self, ins: 'LoadedInstruction'):
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ASSERT_LEN(ins.args, 3)
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dst = ins.get_reg(0)
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src1 = ins.get_reg(1)
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src2 = ins.get_reg(2)
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self.regs.set(
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dst,
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self.regs.get(src1) - self.regs.get(src2)
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)
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def __instruction_lui(self, ins: 'LoadedInstruction'):
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INS_NOT_IMPLEMENTED(ins)
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def __instruction_auipc(self, ins: 'LoadedInstruction'):
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INS_NOT_IMPLEMENTED(ins)
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def __instruction_xor(self, ins: 'LoadedInstruction'):
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ASSERT_LEN(ins.args, 3)
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dst = ins.get_reg(0)
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src1 = ins.get_reg(1)
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src2 = ins.get_reg(2)
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self.regs.set(
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dst,
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self.regs.get(src1) ^ self.regs.get(src2)
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)
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def __instruction_xori(self, ins: 'LoadedInstruction'):
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INS_NOT_IMPLEMENTED(ins)
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def __instruction_or(self, ins: 'LoadedInstruction'):
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ASSERT_LEN(ins.args, 3)
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dst = ins.get_reg(0)
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src1 = ins.get_reg(1)
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src2 = ins.get_reg(2)
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self.regs.set(
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dst,
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self.regs.get(src1) | self.regs.get(src2)
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)
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def __instruction_ori(self, ins: 'LoadedInstruction'):
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INS_NOT_IMPLEMENTED(ins)
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def __instruction_and(self, ins: 'LoadedInstruction'):
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ASSERT_LEN(ins.args, 3)
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dst = ins.get_reg(0)
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src1 = ins.get_reg(1)
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src2 = ins.get_reg(2)
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self.regs.set(
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dst,
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self.regs.get(src1) & self.regs.get(src2)
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)
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def __instruction_andi(self, ins: 'LoadedInstruction'):
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INS_NOT_IMPLEMENTED(ins)
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def __instruction_slt(self, ins: 'LoadedInstruction'):
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ASSERT_LEN(ins.args, 3)
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dst = ins.get_reg(0)
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src1 = ins.get_reg(1)
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src2 = ins.get_reg(2)
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self.regs.set(
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dst,
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int(self.regs.get(src1) < self.regs.get(src2))
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)
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def __instruction_slti(self, ins: 'LoadedInstruction'):
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INS_NOT_IMPLEMENTED(ins)
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def __instruction_sltu(self, ins: 'LoadedInstruction'):
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ASSERT_LEN(ins.args, 3)
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dst = ins.get_reg(0)
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src1 = ins.get_reg(1)
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src2 = ins.get_reg(2)
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self.regs.set(
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dst,
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int(to_unsigned(self.regs.get(src1)) < to_unsigned(self.regs.get(src2)))
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)
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def __instruction_sltiu(self, ins: 'LoadedInstruction'):
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INS_NOT_IMPLEMENTED(ins)
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def __instruction_beq(self, ins: 'LoadedInstruction'):
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ASSERT_LEN(ins.args, 3)
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reg1 = ins.get_reg(0)
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reg2 = ins.get_reg(1)
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dest = ins.get_imm(2)
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if self.regs.get(reg1) == self.regs.get(reg2):
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self.pc = dest
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def __instruction_bne(self, ins: 'LoadedInstruction'):
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ASSERT_LEN(ins.args, 3)
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reg1 = ins.get_reg(0)
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reg2 = ins.get_reg(1)
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dest = ins.get_imm(2)
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if self.regs.get(reg1) != self.regs.get(reg2):
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self.pc = dest
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def __instruction_blt(self, ins: 'LoadedInstruction'):
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ASSERT_LEN(ins.args, 3)
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reg1 = ins.get_reg(0)
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reg2 = ins.get_reg(1)
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dest = ins.get_imm(2)
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if self.regs.get(reg1) < self.regs.get(reg2):
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self.pc = dest
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def __instruction_bge(self, ins: 'LoadedInstruction'):
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ASSERT_LEN(ins.args, 3)
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reg1 = ins.get_reg(0)
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reg2 = ins.get_reg(1)
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dest = ins.get_imm(2)
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if self.regs.get(reg1) >= self.regs.get(reg2):
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self.pc = dest
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def __instruction_bltu(self, ins: 'LoadedInstruction'):
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ASSERT_LEN(ins.args, 3)
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reg1 = to_unsigned(ins.get_reg(0))
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reg2 = to_unsigned(ins.get_reg(1))
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dest = ins.get_imm(2)
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if self.regs.get(reg1) < self.regs.get(reg2):
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self.pc = dest
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def __instruction_bgeu(self, ins: 'LoadedInstruction'):
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ASSERT_LEN(ins.args, 3)
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reg1 = to_unsigned(ins.get_reg(0))
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reg2 = to_unsigned(ins.get_reg(1))
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dest = ins.get_imm(2)
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if self.regs.get(reg1) >= self.regs.get(reg2):
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self.pc = dest
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def __instruction_j(self, ins: 'LoadedInstruction'):
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ASSERT_LEN(ins.args, 1)
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addr = ins.get_imm(0)
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self.pc = addr
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def __instruction_jal(self, ins: 'LoadedInstruction'):
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reg = 'ra' # default register is ra
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if len(ins.args) == 1:
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addr = ins.get_imm(0)
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else:
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ASSERT_LEN(ins.args, 2)
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reg = ins.get_reg(0)
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addr = ins.get_imm(1)
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self.regs.set(reg, self.pc)
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self.pc = addr
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def __instruction_jalr(self, ins: 'LoadedInstruction'):
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ASSERT_LEN(ins.args, 2)
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reg = ins.get_reg(0)
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addr = ins.get_imm(1)
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self.regs.set(reg, self.pc)
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self.pc = addr
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def __instruction_ret(self, ins: 'LoadedInstruction'):
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ASSERT_LEN(ins.args, 0)
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self.pc = self.regs.get('ra')
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def __instruction_ecall(self, ins: 'LoadedInstruction'):
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self.__instruction_scall(ins)
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def __instruction_ebreak(self, ins: 'LoadedInstruction'):
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self.__instruction_sbreak(ins)
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def __instruction_scall(self, ins: 'LoadedInstruction'):
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ASSERT_LEN(ins.args, 0)
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syscall = Syscall(self.regs.get('a7'), self.regs, self)
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self.syscall_int.handle_syscall(syscall)
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def __instruction_sbreak(self, ins: 'LoadedInstruction'):
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launch_debug_session(self, self.mmu, self.regs, "Debug instruction encountered at 0x{:08X}".format(self.pc))
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def __instruction_nop(self, ins: 'LoadedInstruction'):
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pass
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@staticmethod
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def all_instructions():
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for method in vars(CPU):
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if method.startswith('_CPU__instruction_'):
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yield method[18:]
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def all_instructions(self) -> List[str]:
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return list(self.instructions.keys())
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def __repr__(self):
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return "CPU(pc=0x{:08X}, cycle={})".format(
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return "CPU(pc=0x{:08X}, cycle={}, instructions={})".format(
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self.pc,
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self.cycle
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self.cycle,
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" ".join(s.name for s in self.sets)
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)
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46
riscemu/Instructions/InstructionSet.py
Normal file
46
riscemu/Instructions/InstructionSet.py
Normal file
@ -0,0 +1,46 @@
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import typing
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from abc import ABC, abstractmethod
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from ..CPU import *
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class InstructionSet(ABC):
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"""
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Represents a collection of instructions
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"""
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def __init__(self, name):
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self.name = name
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self.cpu: typing.Optional['CPU'] = None
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self.mmu: typing.Optional['MMU'] = None
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self.regs: typing.Optional['Registers'] = None
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|
||||
def load(self, cpu: 'CPU'):
|
||||
self.cpu = cpu
|
||||
self.mmu = cpu.mmu
|
||||
self.regs = cpu.regs
|
||||
|
||||
return {
|
||||
name: ins for name, ins in self.get_instructions()
|
||||
}
|
||||
|
||||
def get_instructions(self):
|
||||
for member in dir(self):
|
||||
if member.startswith('instruction_'):
|
||||
yield member[12:].replace('_', '.'), getattr(self, member)
|
||||
|
||||
def parse_mem_ins(self, ins: 'LoadedInstruction'):
|
||||
return self.cpu.parse_mem_ins(ins)
|
||||
|
||||
@property
|
||||
def pc(self):
|
||||
return self.cpu.pc
|
||||
|
||||
@pc.setter
|
||||
def pc(self, val):
|
||||
self.cpu.pc = val
|
||||
|
||||
def __repr__(self):
|
||||
return "InstructionSet[{}] with {} instructions".format(
|
||||
self.name,
|
||||
len(list(self.get_instructions()))
|
||||
)
|
||||
293
riscemu/Instructions/RV32I.py
Normal file
293
riscemu/Instructions/RV32I.py
Normal file
@ -0,0 +1,293 @@
|
||||
from .InstructionSet import *
|
||||
|
||||
from ..helpers import int_from_bytes, int_to_bytes, to_unsigned, to_signed
|
||||
|
||||
class RV32I(InstructionSet):
|
||||
def __init__(self):
|
||||
super().__init__('RV32I')
|
||||
|
||||
def instruction_lb(self, ins: 'LoadedInstruction'):
|
||||
rd, addr = self.parse_mem_ins(ins)
|
||||
self.regs.set(rd, int_from_bytes(self.mmu.read(addr, 1)))
|
||||
|
||||
def instruction_lh(self, ins: 'LoadedInstruction'):
|
||||
rd, addr = self.parse_mem_ins(ins)
|
||||
self.regs.set(rd, int_from_bytes(self.mmu.read(addr, 2)))
|
||||
|
||||
def instruction_lw(self, ins: 'LoadedInstruction'):
|
||||
rd, addr = self.parse_mem_ins(ins)
|
||||
self.regs.set(rd, int_from_bytes(self.mmu.read(addr, 4)))
|
||||
|
||||
def instruction_lbu(self, ins: 'LoadedInstruction'):
|
||||
rd, addr = self.parse_mem_ins(ins)
|
||||
self.regs.set(rd, int_from_bytes(self.mmu.read(addr, 1), unsigned=True))
|
||||
|
||||
def instruction_lhu(self, ins: 'LoadedInstruction'):
|
||||
rd, addr = self.parse_mem_ins(ins)
|
||||
self.regs.set(rd, int_from_bytes(self.mmu.read(addr, 2), unsigned=True))
|
||||
|
||||
def instruction_sb(self, ins: 'LoadedInstruction'):
|
||||
rd, addr = self.parse_mem_ins(ins)
|
||||
self.mmu.write(addr, 1, int_to_bytes(self.regs.get(rd), 1))
|
||||
|
||||
def instruction_sh(self, ins: 'LoadedInstruction'):
|
||||
rd, addr = self.parse_mem_ins(ins)
|
||||
self.mmu.write(addr, 2, int_to_bytes(self.regs.get(rd), 2))
|
||||
|
||||
def instruction_sw(self, ins: 'LoadedInstruction'):
|
||||
rd, addr = self.parse_mem_ins(ins)
|
||||
self.mmu.write(addr, 4, int_to_bytes(self.regs.get(rd), 4))
|
||||
|
||||
def instruction_sll(self, ins: 'LoadedInstruction'):
|
||||
ASSERT_LEN(ins.args, 3)
|
||||
dst = ins.get_reg(0)
|
||||
src1 = ins.get_reg(1)
|
||||
src2 = ins.get_reg(2)
|
||||
self.regs.set(
|
||||
dst,
|
||||
to_signed(to_unsigned(self.regs.get(src1)) << (self.regs.get(src2) & 0b11111))
|
||||
)
|
||||
|
||||
def instruction_slli(self, ins: 'LoadedInstruction'):
|
||||
ASSERT_LEN(ins.args, 3)
|
||||
dst = ins.get_reg(0)
|
||||
src1 = ins.get_reg(1)
|
||||
imm = ins.get_imm(2)
|
||||
self.regs.set(
|
||||
dst,
|
||||
to_signed(to_unsigned(self.regs.get(src1)) << (imm & 0b11111))
|
||||
)
|
||||
|
||||
def instruction_srl(self, ins: 'LoadedInstruction'):
|
||||
ASSERT_LEN(ins.args, 3)
|
||||
dst = ins.get_reg(0)
|
||||
src1 = ins.get_reg(1)
|
||||
src2 = ins.get_reg(2)
|
||||
self.regs.set(
|
||||
dst,
|
||||
to_signed(to_unsigned(self.regs.get(src1)) >> (self.regs.get(src2) & 0b11111))
|
||||
)
|
||||
|
||||
def instruction_srli(self, ins: 'LoadedInstruction'):
|
||||
ASSERT_LEN(ins.args, 3)
|
||||
dst = ins.get_reg(0)
|
||||
src1 = ins.get_reg(1)
|
||||
imm = ins.get_imm(2)
|
||||
self.regs.set(
|
||||
dst,
|
||||
to_signed(to_unsigned(self.regs.get(src1)) >> (imm & 0b11111))
|
||||
)
|
||||
|
||||
def instruction_sra(self, ins: 'LoadedInstruction'):
|
||||
ASSERT_LEN(ins.args, 3)
|
||||
dst = ins.get_reg(0)
|
||||
src1 = ins.get_reg(1)
|
||||
src2 = ins.get_reg(2)
|
||||
self.regs.set(
|
||||
dst,
|
||||
self.regs.get(src1) >> (self.regs.get(src2) & 0b11111)
|
||||
)
|
||||
|
||||
def instruction_srai(self, ins: 'LoadedInstruction'):
|
||||
ASSERT_LEN(ins.args, 3)
|
||||
dst = ins.get_reg(0)
|
||||
src1 = ins.get_reg(1)
|
||||
imm = ins.get_imm(2)
|
||||
self.regs.set(
|
||||
dst,
|
||||
self.regs.get(src1) >> (imm & 0b11111)
|
||||
)
|
||||
|
||||
def instruction_add(self, ins: 'LoadedInstruction'):
|
||||
ASSERT_LEN(ins.args, 3)
|
||||
dst = ins.get_reg(0)
|
||||
src1 = ins.get_reg(1)
|
||||
src2 = ins.get_reg(2)
|
||||
self.regs.set(
|
||||
dst,
|
||||
self.regs.get(src1) + self.regs.get(src2)
|
||||
)
|
||||
|
||||
def instruction_addi(self, ins: 'LoadedInstruction'):
|
||||
ASSERT_LEN(ins.args, 3)
|
||||
dst = ins.get_reg(0)
|
||||
src1 = ins.get_reg(1)
|
||||
imm = ins.get_imm(2)
|
||||
self.regs.set(
|
||||
dst,
|
||||
self.regs.get(src1) + imm
|
||||
)
|
||||
|
||||
def instruction_sub(self, ins: 'LoadedInstruction'):
|
||||
ASSERT_LEN(ins.args, 3)
|
||||
dst = ins.get_reg(0)
|
||||
src1 = ins.get_reg(1)
|
||||
src2 = ins.get_reg(2)
|
||||
self.regs.set(
|
||||
dst,
|
||||
self.regs.get(src1) - self.regs.get(src2)
|
||||
)
|
||||
|
||||
def instruction_lui(self, ins: 'LoadedInstruction'):
|
||||
INS_NOT_IMPLEMENTED(ins)
|
||||
|
||||
def instruction_auipc(self, ins: 'LoadedInstruction'):
|
||||
INS_NOT_IMPLEMENTED(ins)
|
||||
|
||||
def instruction_xor(self, ins: 'LoadedInstruction'):
|
||||
ASSERT_LEN(ins.args, 3)
|
||||
dst = ins.get_reg(0)
|
||||
src1 = ins.get_reg(1)
|
||||
src2 = ins.get_reg(2)
|
||||
self.regs.set(
|
||||
dst,
|
||||
self.regs.get(src1) ^ self.regs.get(src2)
|
||||
)
|
||||
|
||||
def instruction_xori(self, ins: 'LoadedInstruction'):
|
||||
INS_NOT_IMPLEMENTED(ins)
|
||||
|
||||
def instruction_or(self, ins: 'LoadedInstruction'):
|
||||
ASSERT_LEN(ins.args, 3)
|
||||
dst = ins.get_reg(0)
|
||||
src1 = ins.get_reg(1)
|
||||
src2 = ins.get_reg(2)
|
||||
self.regs.set(
|
||||
dst,
|
||||
self.regs.get(src1) | self.regs.get(src2)
|
||||
)
|
||||
|
||||
def instruction_ori(self, ins: 'LoadedInstruction'):
|
||||
INS_NOT_IMPLEMENTED(ins)
|
||||
|
||||
def instruction_and(self, ins: 'LoadedInstruction'):
|
||||
ASSERT_LEN(ins.args, 3)
|
||||
dst = ins.get_reg(0)
|
||||
src1 = ins.get_reg(1)
|
||||
src2 = ins.get_reg(2)
|
||||
self.regs.set(
|
||||
dst,
|
||||
self.regs.get(src1) & self.regs.get(src2)
|
||||
)
|
||||
|
||||
def instruction_andi(self, ins: 'LoadedInstruction'):
|
||||
INS_NOT_IMPLEMENTED(ins)
|
||||
|
||||
def instruction_slt(self, ins: 'LoadedInstruction'):
|
||||
ASSERT_LEN(ins.args, 3)
|
||||
dst = ins.get_reg(0)
|
||||
src1 = ins.get_reg(1)
|
||||
src2 = ins.get_reg(2)
|
||||
self.regs.set(
|
||||
dst,
|
||||
int(self.regs.get(src1) < self.regs.get(src2))
|
||||
)
|
||||
|
||||
def instruction_slti(self, ins: 'LoadedInstruction'):
|
||||
INS_NOT_IMPLEMENTED(ins)
|
||||
|
||||
def instruction_sltu(self, ins: 'LoadedInstruction'):
|
||||
ASSERT_LEN(ins.args, 3)
|
||||
dst = ins.get_reg(0)
|
||||
src1 = ins.get_reg(1)
|
||||
src2 = ins.get_reg(2)
|
||||
self.regs.set(
|
||||
dst,
|
||||
int(to_unsigned(self.regs.get(src1)) < to_unsigned(self.regs.get(src2)))
|
||||
)
|
||||
|
||||
def instruction_sltiu(self, ins: 'LoadedInstruction'):
|
||||
INS_NOT_IMPLEMENTED(ins)
|
||||
|
||||
def instruction_beq(self, ins: 'LoadedInstruction'):
|
||||
ASSERT_LEN(ins.args, 3)
|
||||
reg1 = ins.get_reg(0)
|
||||
reg2 = ins.get_reg(1)
|
||||
dest = ins.get_imm(2)
|
||||
if self.regs.get(reg1) == self.regs.get(reg2):
|
||||
self.pc = dest
|
||||
|
||||
def instruction_bne(self, ins: 'LoadedInstruction'):
|
||||
ASSERT_LEN(ins.args, 3)
|
||||
reg1 = ins.get_reg(0)
|
||||
reg2 = ins.get_reg(1)
|
||||
dest = ins.get_imm(2)
|
||||
if self.regs.get(reg1) != self.regs.get(reg2):
|
||||
self.pc = dest
|
||||
|
||||
def instruction_blt(self, ins: 'LoadedInstruction'):
|
||||
ASSERT_LEN(ins.args, 3)
|
||||
reg1 = ins.get_reg(0)
|
||||
reg2 = ins.get_reg(1)
|
||||
dest = ins.get_imm(2)
|
||||
if self.regs.get(reg1) < self.regs.get(reg2):
|
||||
self.pc = dest
|
||||
|
||||
def instruction_bge(self, ins: 'LoadedInstruction'):
|
||||
ASSERT_LEN(ins.args, 3)
|
||||
reg1 = ins.get_reg(0)
|
||||
reg2 = ins.get_reg(1)
|
||||
dest = ins.get_imm(2)
|
||||
if self.regs.get(reg1) >= self.regs.get(reg2):
|
||||
self.pc = dest
|
||||
|
||||
def instruction_bltu(self, ins: 'LoadedInstruction'):
|
||||
ASSERT_LEN(ins.args, 3)
|
||||
reg1 = to_unsigned(ins.get_reg(0))
|
||||
reg2 = to_unsigned(ins.get_reg(1))
|
||||
dest = ins.get_imm(2)
|
||||
if self.regs.get(reg1) < self.regs.get(reg2):
|
||||
self.pc = dest
|
||||
|
||||
def instruction_bgeu(self, ins: 'LoadedInstruction'):
|
||||
ASSERT_LEN(ins.args, 3)
|
||||
reg1 = to_unsigned(ins.get_reg(0))
|
||||
reg2 = to_unsigned(ins.get_reg(1))
|
||||
dest = ins.get_imm(2)
|
||||
if self.regs.get(reg1) >= self.regs.get(reg2):
|
||||
self.pc = dest
|
||||
|
||||
# technically deprecated
|
||||
def instruction_j(self, ins: 'LoadedInstruction'):
|
||||
ASSERT_LEN(ins.args, 1)
|
||||
addr = ins.get_imm(0)
|
||||
self.pc = addr
|
||||
|
||||
def instruction_jal(self, ins: 'LoadedInstruction'):
|
||||
reg = 'ra' # default register is ra
|
||||
if len(ins.args) == 1:
|
||||
addr = ins.get_imm(0)
|
||||
else:
|
||||
ASSERT_LEN(ins.args, 2)
|
||||
reg = ins.get_reg(0)
|
||||
addr = ins.get_imm(1)
|
||||
self.regs.set(reg, self.pc)
|
||||
self.pc = addr
|
||||
|
||||
def instruction_jalr(self, ins: 'LoadedInstruction'):
|
||||
ASSERT_LEN(ins.args, 2)
|
||||
reg = ins.get_reg(0)
|
||||
addr = ins.get_imm(1)
|
||||
self.regs.set(reg, self.pc)
|
||||
self.pc = addr
|
||||
|
||||
def instruction_ret(self, ins: 'LoadedInstruction'):
|
||||
ASSERT_LEN(ins.args, 0)
|
||||
self.pc = self.regs.get('ra')
|
||||
|
||||
def instruction_ecall(self, ins: 'LoadedInstruction'):
|
||||
self.instruction_scall(ins)
|
||||
|
||||
def instruction_ebreak(self, ins: 'LoadedInstruction'):
|
||||
self.instruction_sbreak(ins)
|
||||
|
||||
def instruction_scall(self, ins: 'LoadedInstruction'):
|
||||
ASSERT_LEN(ins.args, 0)
|
||||
syscall = Syscall(self.regs.get('a7'), self.regs, self.cpu)
|
||||
self.cpu.syscall_int.handle_syscall(syscall)
|
||||
|
||||
def instruction_sbreak(self, ins: 'LoadedInstruction'):
|
||||
launch_debug_session(self.cpu, self.mmu, self.regs, "Debug instruction encountered at 0x{:08X}".format(self.pc))
|
||||
|
||||
def instruction_nop(self, ins: 'LoadedInstruction'):
|
||||
pass
|
||||
0
riscemu/Instructions/__init__.py
Normal file
0
riscemu/Instructions/__init__.py
Normal file
@ -2,13 +2,8 @@ import re
|
||||
from enum import IntEnum
|
||||
from typing import List
|
||||
|
||||
from .CPU import CPU, Registers
|
||||
from .Exceptions import ParseException
|
||||
|
||||
REGISTERS = list(Registers.all_registers())
|
||||
|
||||
INSTRUCTIONS = list(CPU.all_instructions())
|
||||
|
||||
PSEUDO_OPS = [
|
||||
'.asciiz',
|
||||
'.double',
|
||||
@ -245,10 +240,11 @@ class RiscVPseudoOpToken(RiscVToken):
|
||||
|
||||
|
||||
class RiscVTokenizer:
|
||||
def __init__(self, input: RiscVInput):
|
||||
def __init__(self, input: RiscVInput, instructions: List[str]):
|
||||
self.input = input
|
||||
self.tokens: List[RiscVToken] = []
|
||||
self.name = input.name
|
||||
self.instructions = instructions
|
||||
|
||||
def tokenize(self):
|
||||
while self.input.has_next():
|
||||
@ -268,7 +264,7 @@ class RiscVTokenizer:
|
||||
self.parse_comment()
|
||||
|
||||
# must be instruction
|
||||
elif self.input.peek_one_of(INSTRUCTIONS):
|
||||
elif self.input.peek_one_of(self.instructions):
|
||||
self.parse_instruction()
|
||||
else:
|
||||
token = self.input.peek(size=5)
|
||||
@ -295,7 +291,7 @@ class RiscVTokenizer:
|
||||
self.input.context()))
|
||||
|
||||
def parse_instruction(self):
|
||||
ins = self.input.consume_one_of(INSTRUCTIONS)
|
||||
ins = self.input.consume_one_of(self.instructions)
|
||||
args = []
|
||||
self.input.consume_whitespace(linebreak=False)
|
||||
while self.input.peek(regex=REG_VALID_ARGUMENT) and len(args) < 3:
|
||||
|
||||
@ -1,6 +1,7 @@
|
||||
if __name__ == '__main__':
|
||||
from . import *
|
||||
from .helpers import *
|
||||
from .Instructions.RV32I import RV32I
|
||||
import argparse
|
||||
import sys
|
||||
|
||||
@ -60,10 +61,10 @@ if __name__ == '__main__':
|
||||
FMT_PRINT = FMT_BOLD + FMT_MAGENTA
|
||||
|
||||
try:
|
||||
cpu = CPU(cfg)
|
||||
cpu = CPU(cfg, [RV32I()])
|
||||
loaded_exe = None
|
||||
for file in args.files:
|
||||
tk = RiscVTokenizer(RiscVInput.from_file(file))
|
||||
tk = cpu.get_tokenizer(RiscVInput.from_file(file))
|
||||
tk.tokenize()
|
||||
loaded_exe = cpu.load(ExecutableParser(tk).parse())
|
||||
# run the last loaded executable
|
||||
|
||||
Loading…
Reference in New Issue
Block a user